📄 reg5087.ho
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/******************************************************************************/
/* SCCS: %Z% Name: %M% Date US: %G% %U% Ver.: %I% */
/******************************************************************************/
/*F(***************************************************************************
* File name : %M%
* Project : X15
* Module : LGB/SYS reg5087.ho
* Date : (US) %G% %U%
* Version : %I%
* Compiler name and release(s) :
*----------------------------------------------------------------------------*
*----------------------------------------------------------------------------*
* DESCRIPTION
*
*----------------------------------------------------------------------------*
* This file contains the define for the register of the 5087:
* all registers name begin by PCF5087_
*----------------------------------------------------------------------------*
* FUNCTIONS DEFINED IN THIS FILE
*----------------------------------------------------------------------------*
* Name | Object
*----------------------------------------------------------------------------*
*
*----------------------------------------------------------------------------*
*----------------------------------------------------------------------------*
* EVOLUTION
*----------------------------------------------------------------------------*
* Date | Author | Arnb | Description
*----------------------------------------------------------------------------*
* 25-03-98 | A. Rosay | XXYYYY | creation
*----------------------------------------------------------------------------*
* 06-12-02 | tcmc_fro | XXYYYY | CR1194: Change in reg5087.ho requested
* for RRM NEXE host testing
***************************************************************************)F*/
/* #*/
#ifndef REG5087_H
#define REG5087_H
#define ZEROS 0
#define BIT0 0x00000001
#define BIT1 0x00000002
#define BIT2 0x00000004
#define BIT3 0x00000008
#define BIT4 0x00000010
#define BIT5 0x00000020
#define BIT6 0x00000040
#define BIT7 0x00000080
#define BIT8 0x00000100
#define BIT9 0x00000200
#define BIT10 0x00000400
#define BIT11 0x00000800
#define BIT12 0x00001000
#define BIT13 0x00002000
#define BIT14 0x00004000
#define BIT15 0x00008000
#define BIT16 0x00010000
#define BIT17 0x00020000
#define BIT18 0x00040000
#define BIT19 0x00080000
#define BIT20 0x00100000
#define BIT21 0x00200000
#define BIT22 0x00400000
#define BIT23 0x00800000
#define BIT24 0x01000000
#define BIT25 0x02000000
#define BIT26 0x04000000
#define BIT27 0x08000000
#define BIT28 0x10000000
#define BIT29 0x20000000
#define BIT30 0x40000000
#define BIT31 0x80000000 /* DGE : solves a compilation warning */
/**********************************************************************/
/*------------*/
/* UART0 UNIT */
/*------------*/
#if defined (__arm) || defined(_LABWIN32) || defined(__BORLANDC__)
#define PCF5087_U0SCON1 *( ( volatile u8 *) ( 0xFFFF9003 ) )
#define PCF5087_U0SCON2 *( ( volatile u8 *) ( 0xFFFF9002 ) )
#define PCF5087_U0SCON3 *( ( volatile u8 *) ( 0xFFFF9007 ) )
#define PCF5087_U0SCON4 *( ( volatile u8 *) ( 0xFFFF9006 ) )
#define PCF5087_U0BCON *( ( volatile u8 *) ( 0xFFFF900B ) )
#define PCF5087_U0BREGH *( ( volatile u8 *) ( 0xFFFF900E ) )
#define PCF5087_U0BREGL *( ( volatile u8 *) ( 0xFFFF900F ) )
#define PCF5087_U0SBUF *( ( volatile u8 *) ( 0xFFFF9013 ) )
#define PCF5087_U0RM *( ( volatile u8 *) ( 0xFFFF9017 ) )
#if defined(__PCF50872__)
#define PCF5087_U0RM_A *( ( volatile u8 *) ( 0xFFFF901B ) )
#endif /* #if defined(__PCF50872__) */
#endif
/* PCF5087_U0BCON */
#define CTS_BIT ( BIT2 ) /* CTS pin */
#define RTS_BIT ( BIT3 ) /* RTS pin */
/* PCF5087_U0SCON1 */
#define MODE3 ( BIT7 | BIT6 ) /* shift register CLK/6 */
#define MODE2 ( BIT7 ) /* 8-bit UART BGCLK0-1 */
#define MODE1 ( BIT6 ) /* 9-bit UART CLK/16 */
#define MODE0 ZEROS /* 9-bit UART BGCLK0-1
RESET STATE */
#define SM2 ( BIT5 ) /* Multiprocessor bit - RESET STATE = 0 */
#define REN ( BIT4 ) /* Receive enable - RESET STATE = 0.
The receive is enabled when REN is set */
#define TB8 ( BIT3 ) /* Transmit extra bit: 9th data bit that will be transmitted in mode 2 and 3 */
/* RESET STATE = 0 */
#define RB8 ( BIT2 ) /* Receive extra bit: 9th data bit that will be received in mode 2 and 3 */
/* in mode 1 if SM2 = 0, RB8 is the stop bit wich is received */
/* RESET STATE = 0 */
#define TI ( BIT1 ) /* transmit interrupt flag, set by hardware at the end of the 8th bit time */
/* in mode 0, or halfway through the stop bit in other modes */
#define RI ( BIT0 ) /* receive interrupt flag, set by hardware at the end of the 8th bit time */
/* in mode 0, or halfway through the stop bit in other modes */
#define U0_MODE3 ( BIT7 | BIT6 ) /* shift register CLK/6 */
#define U0_MODE2 ( BIT7 ) /* 8-bit UART BGCLK0-1 */
#define U0_MODE1 ( BIT6 ) /* 9-bit UART CLK/16 */
#define U0_MODE0 ZEROS /* 9-bit UART BGCLK0-1
RESET STATE */
#define U0_SM2 ( BIT5 ) /* Multiprocessor bit - RESET STATE = 0 */
#define U0_REN ( BIT4 ) /* Receive enable - RESET STATE = 0.
The receive is enabled when REN is set */
#define U0_TB8 ( BIT3 ) /* Transmit extra bit: 9th data bit that will be transmitted in mode 2 and 3 */
/* RESET STATE = 0 */
#define U0_RB8 ( BIT2 ) /* Receive extra bit: 9th data bit that will be received in mode 2 and 3 */
/* in mode 1 if SM2 = 0, RB8 is the stop bit wich is received */
/* RESET STATE = 0 */
#define U0_TI ( BIT1 ) /* transmit interrupt flag, set by hardware at the end of the 8th bit time */
/* in mode 0, or halfway through the stop bit in other modes */
#define U0_RI ( BIT0 ) /* receive interrupt flag, set by hardware at the end of the 8th bit time */
/* in mode 0, or halfway through the stop bit in other modes */
/* PCF5087_U0SCON2 */
#define FEF ( BIT7 ) /* Framing Error Flag */
#define OEF ( BIT6 ) /* Overrun Error Flag */
#define PEF ( BIT5 ) /* Parity Error Flag */
#define FEN ( BIT4 ) /* Enable Framing Error Check bit */
#define OEN ( BIT3 ) /* Enable Overrun Error Check bit */
#define ODDP ZEROS /* odd parity */ /*RESET STATE */
#define EVENP ( BIT1 ) /* even parity */
#define MARKP ( BIT2 ) /* mark parity */
#define SPACEP ( BIT2 | BIT1 ) /* space parity */
#define PE ( BIT0 ) /* Parity Enable Bit */
#define U0_FEF ( BIT7 ) /* Framing Error Flag */
#define U0_OEF ( BIT6 ) /* Overrun Error Flag */
#define U0_PEF ( BIT5 ) /* Parity Error Flag */
#define U0_FEN ( BIT4 ) /* Enable Framing Error Check bit */
#define U0_OEN ( BIT3 ) /* Enable Overrun Error Check bit */
#define U0_ODDP ZEROS /* odd parity */ /*RESET STATE */
#define U0_EVENP ( BIT1 ) /* even parity */
#define U0_MARKP ( BIT2 ) /* mark parity */
#define U0_SPACEP ( BIT2 | BIT1 ) /* space parity */
#define U0_PE ( BIT0 ) /* Parity Enable Bit */
/* PCF5087_U0SCON3 */
#define SIREN ( BIT7 ) /* 0 : No SIR interface function for TxD0 and RxD0 */
/* 1 : Pulse shaping function used in IrDA standard application */
#define RTSEN ( BIT6 ) /* RTS control Enable */
#define CTSEN ( BIT5 ) /* 1 : CTS0_N input control the operation of the transmitter */
/* 0 : CTS0_N has no influnce on the transmitter */
#define LOOP ( BIT4 ) /* set channel mode , RESET STATE 0 */
/* LOOP = 0 : normal mode, LOOP = 1 : local loopback */
#define BI ( BIT3 ) /* break interrupt indicator */
#define BEN ( BIT2 ) /* 0 : Break detection disable */
/* 1 : Break detection enable */
#define SB ( BIT1 ) /* Break control bit */
/* 0 : force a break condition ; 1 : disabled break condition*/
#define STB ( BIT0 ) /* The Number of stop bits transmitted and received */
/* U0STB = 0 : One stop bit */
/* U0STB = 1 : Two stop bit */
#define U0_SIREN ( BIT7 ) /* 0 : No SIR interface function for TxD0 and RxD0 */
/* 1 : Pulse shaping function used in IrDA standard application */
#define U0_RTSEN ( BIT6 ) /* RTS control Enable */
#define U0_CTSEN ( BIT5 ) /* 1 : CTS0_N input control the operation of the transmitter */
/* 0 : CTS0_N has no influnce on the transmitter */
#define U0_LOOP ( BIT4 ) /* set channel mode , RESET STATE 0 */
/* LOOP = 0 : normal mode, LOOP = 1 : local loopback */
#define U0_BI ( BIT3 ) /* break interrupt indicator */
#define U0_BEN ( BIT2 ) /* 0 : Break detection disable */
/* 1 : Break detection enable */
#define U0_SB ( BIT1 ) /* Break control bit */
/* 0 : force a break condition ; 1 : disabled break condition*/
#define U0_STB ( BIT0 ) /* The Number of stop bits transmitted and received */
/* U0STB = 0 : One stop bit */
/* U0STB = 1 : Two stop bit */
/* PCF5087_U0SCON4 */
#define RMF ( BIT2 ) /* Reception match flag : set at the reception of a matching character */
/* it must be cleared by software */
#define RME ( BIT1 ) /* 1 : Enable the register match function */
/* 0 : Disable the register match function */
#define U0_CTSF ( BIT7 )
#define U0_RMF_A ( BIT6 ) /* Alternative reception match flag : set at the reception of a matching character */
/* it must be cleared by software */
#define U0_RME_A ( BIT5 ) /* 1 : Enable the alternative reception match function */
/* 0 : Disable the alternative reception match function */
#define U0_WUPF ( BIT4 ) /* Wake-up flag : set at high to low transition in RxD0 while sleep or stop mode */
#define U0_WUPEN ( BIT3 ) /* 0 : Enable wake-up feature in SIR mode */
/* 0 : Disable wake-up feature in SIR mode */
#define U0_RMF ( BIT2 ) /* Reception match flag : set at the reception of a matching character */
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