91x_enet.h

STR912 arm9实现的以太网通信程序

#define ENET_DSCR_RX_STATUS_MCAST_FR_MSK 0x08000000 /* Multicast Frame */
#define ENET_DSCR_RX_STATUS_BCAST_FR_MSK 0x10000000 /* BroadCast Frame */
#define ENET_DSCR_RX_STATUS_FLT_FAIL_MSK 0x20000000 /* Filtering Fail */
#define ENET_DSCR_RX_STATUS_PKT_FILT_MSK 0x40000000 /* Packet Filter */
#define ENET_DSCR_RX_STATUS_MIS_FR_MSK   0x80000000 /* Missed Frame */
#define ENET_DSCR_RX_STATUS_ERROR_MSK   (ENET_DSCR_RX_STATUS_LEN_ERR | ENET_DSCR_RX_STATUS_CRC_ERR | \
                                        ENET_DSCR_RX_STATUS_MII_ERR | ENET_DSCR_RX_STATUS_RUNTFR |  \
                                        ENET_DSCR_RX_STATUS_FTLONG | ENET_DSCR_RX_STATUS_COLLSEEN)
#define ENET_DSCR_RX_STATUS_ORED_ERR_MSK 0x00000000 /*Mask for total number of errors */
                                                
/* ENET DMA Interrupt Definition */                                                                       
#define ENET_IT_All                     0xFFFFFFFF
#define ENET_IT_TX_CURR_DONE            0x80000000  /*  Tx Current Done interrupt */  
#define ENET_IT_TX_MERR_INT             0x02000000  /*  Tx Master Error interrupt */
#define ENET_IT_TX_DONE                 0x00800000  /*  Tx Done interrupt */
#define ENET_IT_TX_NEXT                 0x00400000  /*  Tx Invalid Next Descriptor interrupt */
#define ENET_IT_TX_TO                   0x00080000  /*  Tx timeout interrupt */
#define ENET_IT_TX_ENTRY                0x00040000  /*  Tx FIFO Entry Error interrupt */ 
#define ENET_IT_TX_FULL                 0x00020000  /*  Tx FIFO Full interrupt */
#define ENET_IT_TX_EMPTY                0x00010000  /*  Tx FIFO Empty interrupt */
#define ENET_IT_RX_CURR_DONE            0x00008000  /*  Rx Current Done interrupt */
#define ENET_IT_RX_MERR_INT             0x00000200  /*  Rx Master Error interrupt */ 
#define ENET_IT_RX_DONE                 0x00000080  /*  Rx Done interrupt */
#define ENET_IT_RX_NEXT                 0x00000040  /*  Rx Invalid Next Descriptor interrupt */ 
#define ENET_IT_PACKET_LOST             0x00000020  /*  Packet Lost interrupt */
#define ENET_IT_RX_TO                   0x00000008  /*  Rx Timeout */
#define ENET_IT_RX_ENTRY                0x00000004  /*  Rx FIFO Entry Error interrupt */
#define ENET_IT_RX_FULL                 0x00000002  /*  Rx FIFO Full interrupt */
#define ENET_IT_RX_EMPTY                0x00000001  /*  Rx FIFO Empty interrupt */

/* ENET_MIIA */
#define ENET_MIIA_PADDR                 0x0000F800  /* Physical address mask */
#define ENET_MIIA_RADDR                 0x000007C0  /* Register address mask */
#define ENET_MIIA_PR                    0x00000004  /* MII Preamble removal */
#define ENET_MIIA_WR                    0x00000002  /* MII Write/Read */
#define ENET_MIIA_BUSY                  0x00000001  /* MII Busy */

/* ENET_MIID */
#define ENET_MIID_RDATA                 0x0000FFFF  /* MII Data */
                                                            
/* MII Read/write Timeouts*/                            
#define MII_READ_TO                     0x0004FFFF      
#define MII_WRITE_TO                    0x0004FFFF    

/*----------------------------------------------------------------------------*/
/*                  Description of common PHY registers                       */
/*----------------------------------------------------------------------------*/
                                                                    
/* Register address */                                  
#define PHY_XCR                          0          /* Tranceiver Control Register */
#define PHY_XSR                          1          /* Tranceiver Status Register */
#define PHY_PID1                         2          /* Tranceiver PHY IDentifier 1 */
#define PHY_PID2                         3          /* Tranceiver PHY IDentifier 2 */
#define PHY_ANA                          4          /* Auto-Negotiation Advertissement register */
#define PHY_ANLPA                        5          /* Auto-Negotiation Link Partner Ability register */
#define PHY_ANE                          6          /* Auto-Negotiation Expansion register */
#define PHY_XCIIS                       17          /* Configuration Information and Interrupt Status */
#define PHY_XIE                         18          /* Interrupt Enable register*/
#define PHY_100CTR                      19          /* 100Base-TX control register */
#define PHY_XMC                         20          /* Mode control */
                                                      
/* XCR, control register */                             
#define PHY_Reset_Control               0x8000      /* PHY Reset */
#define PHY_Loopback                    0x4000      /* Select loop-back mode */
#define PHY_FULLDUPLEX_100M             0x2100      /* Set the full-duplex mode at 100 Mb/s */
#define PHY_HALFDUPLEX_100M             0x2000      /* Set the half-duplex mode at 100 Mb/s */
#define PHY_FULLDUPLEX_10M              0x0100      /* Set the full-duplex mode at 10 Mb/s */
#define PHY_HALFDUPLEX_10M              0x0000      /* Set the half-duplex mode at 10 Mb/s */
#define PHY_AutoNegotiation             0x1000      /* Enable auto-negotiation function */
#define PHY_Restart_AutoNegotiation     0x200       /* Restart auto-negotiation function */
#define PHY_Powerdown                   0x800       /* Select the power down mode */
#define PHY_Isolate                     0x400       /* Isolate PHY from MII */

#define PHY_ResetDelay                  0xFFFFF    

/* XSR, status register */
/* Read only register */                                 
#define PHY_AutoNego_Complete           0x20        /* Auto-Negotioation process completed */
#define PHY_Linked_Status               0x04        /* Valid link established */
#define PHY_Jabber_detection            0x02        /* Jabber condition detected */
                                                      
/* ANLP, Auto-Negotiation Link Partner Ability */
/* Read only register */      
#define PHY_LinkPartner_NextPage        0x8000      /* Link partner with Next page ability */
#define PHY_LinkPartner_ACK             0x4000      /* Link partner Acknowledge */
#define PHY_LinkPartner_Fault           0x2000      /* Link partner's remote fault status */ 
#define PHY_LinkPartner_FlowCtl         0x0400      /* Link partner with PAUSE function ability */
#define PHY_LinkPartner_100T4           0x0200      /* 100BASE-T4 ability */
#define PHY_LinkPartner_100F            0x0100      /* 100M Full duplex ability */
#define PHY_LinkPartner_100H            0x0080      /* 100M Half duplex ability */
#define PHY_LinkPartner_10F             0x0040      /* 10M Full duplex ability */
#define PHY_LinkPartner_10H             0x0020      /* 10M Half duplex ability */
                                                              
/* ANE, Auto-Negotiation expansion */
/* Read only register */                             
#define PHY_ParallelFault               0x10        /* Parallel detection fault */
#define PHY_NextPage                    0x04        /* In case of STE100P this bit is always 0 since it without next page ability */
#define PHY_NewPageRcv                  0x02        /* Page Received */
#define PHY_LinkPartner_AutoNego        0x01        /* Link Partner Auto-Negotiation ability */
                                                        
/* XCIIS, configuration information and interrupt status */
/* Read only register */ 
#define PHY_Configured_Speed            0x200       /* Configured information of Speed */
#define PHY_Configured_Duplex           0x100       /* Configured information of Duplex */
#define PHY_Configured_PAUSE            0x080       /* Configured information of PAUSE function for flow control */
#define PHY_ITSrc_AutoNego_Cmplt        0x040       /* Interrupt source of Auto-Negotiation Completed */
#define PHY_ITSrc_RemoteFault           0x020       /* Interrupt source of Remote Fault Detected */
#define PHY_ITSrc_LinkFail              0x010       /* Interrupt source of Link Fail */
#define PHY_ITSrc_AutoNeg_Ack           0x008       /* Interrupt source of Auto-Negotiation ACK received */
#define PHY_ITSrc_ParallelFault         0x004       /* Interrupt source of Parallel Detection Fault */
#define PHY_ITSrc_AutoNeg_PageRcv       0x002       /* Interrupt source of Auto-Negotiation Page Received */
#define PHY_ITSrc_ErrorFull             0x001       /* Interrupt source of receive Error Full */  
#define PHY_ConfigurationMask           0x380       /* XCIIS Configuration bits Mask */

/* XIE, interrupt enable register */    
#define PHY_IT_AutoNego_Cmplt           0x40        /* Auto-Negotiation Completed interrupt Enable */
#define PHY_IT_RemoteFault              0x20        /* Remote Fault detected interrupt Enable */
#define PHY_IT_LinkFail                 0x10        /* Link Down interrupt Enable */
#define PHY_IT_AutoNeg_Ack              0x08        /* Auto-Negotiation ACK interrupt Enable */
#define PHY_IT_ParallelFault            0x04        /* Parallel Fault Detection interrupt Enable */
#define PHY_IT_AutoNeg_PageRcv          0x02        /* Auto-Negotiation Page Received interrupt Enable */
#define PHY_IT_ErrorFull                0x01        /* Receive Error Full interrupt Enable */

/*----------------------------------------------------------------------------*/
/*                             Structures typedef                             */
/*----------------------------------------------------------------------------*/

/*Struct containing the DMA Descriptor data */
typedef struct  {
  vu32 dmaCntl;                /* DMA Control Register                     */
  vu32 dmaAddr;                /* DMA Start Address Register               */
  vu32 dmaNext;                /* DMA Next Descriptor Register             */
  vu32 dmaPackStatus;          /* DMA Packet Status and Control Register   */
} ENET_DMADSCRBase;

/* ENET_MACConfig Struct*/
typedef struct {
  FunctionalState ReceiveALL;                 /* Receive All frames: no address rule filtering */
  u32             MIIPrescaler;               /* MII Clock Prescaler value */
  FunctionalState LoopbackMode;               /* MAC Loopback mode */
  u32             AddressFilteringMode;       /* Address Filtering Mode */
  u32             VLANFilteringMode;          /* VLAN Filtering Mode */
  FunctionalState PassWrongFrame;             /* Pass wrong frame (CRC, overlength, runt..)*/
  FunctionalState LateCollision;              /* Retransmit frame when late collision*/
  FunctionalState BroadcastFrameReception;    /* Accept broardcast frame */
  FunctionalState PacketRetry;                /* Retransmit frame in case of collision */
  FunctionalState RxFrameFiltering;           /* Filter early runt frame and address filter fail frames*/
  FunctionalState AutomaticPadRemoval;        /* Automatic Padding removal */
  FunctionalState DeferralCheck;              /* Excessive Defferal check */
} ENET_MACConfig;

/* ENET_TxStatus Struct*/
typedef struct {
  FlagStatus PacketRetry;
  u16         ByteCount;
  u8         CollisionCount;
  FlagStatus LateCollisionObserved;
  FlagStatus Deffered;
  FlagStatus UnderRun;
  FlagStatus ExcessiveCollision;
  FlagStatus LateCollision;
  FlagStatus ExcessiveDefferal;
  FlagStatus LossOfCarrier;
  FlagStatus NoCarrier;
  FlagStatus FrameAborted;
} ENET_TxStatus;

/* ENET_RxStatus Struct*/
typedef struct {
  FlagStatus FrameAborted;
  FlagStatus PacketFilter;
  FlagStatus FilteringFail;
  FlagStatus BroadCastFrame;
  FlagStatus MulticastFrame;
  FlagStatus UnsupportedControFrame;
  FlagStatus ControlFrame;
  FlagStatus LengthError;
  FlagStatus Vlan2Tag;
  FlagStatus Vlan1Tag;
  FlagStatus CRCError;
  FlagStatus ExtraBit;
  FlagStatus MIIError;
  FlagStatus FrameType;
  FlagStatus LateCollision;
  FlagStatus OverLength;
  FlagStatus RuntFrame;
  FlagStatus WatchDogTimout;
  FlagStatus FalseCarrierIndication;
  u16        FrameLength;
} ENET_RxStatus;

/*----------------------------------------------------------------------------*/
/*                              Exported variables                            */
/*----------------------------------------------------------------------------*/
extern ENET_DMADSCRBase  dmaRxDscrBase[ENET_RXBUFNB],
                         dmaTxDscrBase[ENET_TXBUFNB];/* Rx & Tx DMA Descriptors */

extern u8 RxBuff[ENET_RXBUFNB][ENET_MAX_PACKET_SIZE], 
          TxBuff[ENET_TXBUFNB][ENET_MAX_PACKET_SIZE];/* ENET buffers */

extern vu8 RxBC, TxBC;/* Rx & Tx Buffers Counters */


/*----------------------------------------------------------------------------*/
/*                        Functions  Prototypes                               */
/*----------------------------------------------------------------------------*/

/** ENET Initializations ******************************************************/
void ENET_Init(ENET_MACConfig *MAC_Config);
void ENET_SetOperatingMode(u32 ENET_OperatingMode);
void ENET_Start(void);

/** ENET frames transfer ******************************************************/
u32 ENET_HandleRxPkt(void *ppkt);
void ENET_UpdateRxDscr(void);
void ENET_HandleTxPkt(void *ppkt, u16 size);
void ENET_UpdateTxDscr(u16 FrameSize);

/** ENET frames status ********************************************************/
void ENET_GetRxStatus(ENET_RxStatus * RxStatus);
void ENET_GetTxStatus(ENET_TxStatus * TxStatus);

/** ENET DMA Interrupt control functions **************************************/
void ENET_ITConfig(u32 ENET_IT, FunctionalState NewState);
u32 ENET_GetITSrc(void);
void ENET_ClearIT(u32 ENET_IT);

/** ENET PHY control **********************************************************/
void ENET_MIIWriteReg (u8 phyDev, u8 phyReg, u32  phyVal);
u32 ENET_MIIReadReg (u8 phyDev, u8 phyReg );
void ENET_PHYITConfig(u8 phyDev, u32 PHY_IT, FunctionalState NewState);
u32 ENET_PHYGetITSrc(u8 phyDev);
void ENET_PHYIsolate(u8 phyDev, FunctionalState NewState);
void ENET_PHYPowerdown(u8 phyDev, FunctionalState NewState);
void ENET_PHYLoopBack(u8 phyDev, FunctionalState NewState);
void ENET_PHYReset(u8 phyDev);


#endif  /* _ENET_H_ */

/******************** (C) COPYRIGHT 2007 STMicroelectronics *******************/