parity_even1.vhd

用VHDL实现3位二进制信息码的并行偶发生及校验电路

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY parity_even1 IS
PORT(a,b,c:IN STD_LOGIC;
     we1:OUT  STD_LOGIC);
END parity_even1;
ARCHITECTURE parity_even1p  OF parity_even1 IS
BEGIN
PROCESS(a,b,c)
BEGIN
we1<=a XOR b XOR c;
END PROCESS;
END parity_even1p ;