parity_even2.vhd

用VHDL实现3位二进制信息码的并行偶发生及校验电路

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY parity_even2 IS
PORT(a,b,c:IN STD_LOGIC;
     we1:IN STD_LOGIC;
     we2:OUT STD_LOGIC);
END parity_even2;
ARCHITECTURE parity_even2p  OF parity_even2 IS
BEGIN
PROCESS(a,b,c,we1)
BEGIN
we2<=NOT(a XOR b XOR c XOR we1);
END PROCESS;
END parity_even2p ;