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📄 ps2.lst

📁 P/S 测试程序
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A51 MACRO ASSEMBLER  PS2                                                                  10/27/2008 11:52:56 PAGE     1


MACRO ASSEMBLER A51 V7.00a
OBJECT MODULE PLACED IN PS2.OBJ
ASSEMBLER INVOKED BY: d:\Keil\C51\BIN\A51.EXE PS2.asm SET(SMALL) DEBUG EP

LOC  OBJ            LINE     SOURCE

  00B4                 1     sbit  _data   = P3.4
  00B3                 2     sbit  _clock  = P3.3
  0000                 3     sbit  _parity = 0x00
                       4     
0000                   5         ORG   0x0000
0000 0102              6         AJMP  Main
0002                   7     Main:
0002 758160            8         MOV   SP,     #0x60
0005                   9     Loop:
                      10     
0005 74E0             11         MOV   A,      #0xe0
0007 A2D0             12         MOV   C,      P
0009 B3               13         CPL   C
000A 9200             14         MOV   _parity,C   ;Init reg for parity calc
000C 1148             15         ACALL CodeOut
000E 7437             16         MOV   A,      #0x37
0010 A2D0             17         MOV   C,      P
0012 B3               18         CPL   C
0013 9200             19         MOV   _parity,C   ;Init reg for parity calc
0015 1148             20         ACALL CodeOut
                      21     
0017 7E00             22         MOV   R6,     #0
0019                  23     De1:
0019 7D00             24         MOV   R5,     #0
001B DDFE             25         DJNZ  R5,     $
001D DEFA             26         DJNZ  R6,     De1
                      27     
001F 74E0             28         MOV   A,      #0xe0
0021 A2D0             29         MOV   C,      P
0023 B3               30         CPL   C
0024 9200             31         MOV   _parity,C   ;Init reg for parity calc
0026 1148             32         ACALL CodeOut
0028 74F0             33         MOV   A,      #0xf0
002A A2D0             34         MOV   C,      P
002C B3               35         CPL   C
002D 9200             36         MOV   _parity,C   ;Init reg for parity calc
002F 1148             37         ACALL CodeOut
0031 7437             38         MOV   A,      #0x37
0033 A2D0             39         MOV   C,      P
0035 B3               40         CPL   C
0036 9200             41         MOV   _parity,C   ;Init reg for parity calc
0038 1148             42         ACALL CodeOut
                      43     
003A 7F08             44         MOV   R7,     #8
003C                  45     Del:
003C 7E00             46         MOV   R6,     #0
003E                  47     De:
003E 7D00             48         MOV   R5,     #0
0040 DDFE             49         DJNZ  R5,     $
0042 DEFA             50         DJNZ  R6,     De
0044 DFF6             51         DJNZ  R7,     Del
0046 0105             52         AJMP  Loop
                      53     
                      54     
0048                  55     CodeOut:
0048 7F08             56         MOV   R7,     #0x08
004A                  57     InhibitLoop:
004A 30B3FD           58         JNB   _clock, InhibitLoop ;Check for inhibit
A51 MACRO ASSEMBLER  PS2                                                                  10/27/2008 11:52:56 PAGE     2

004D 118F             59         ACALL Delay50us           ;Delay 50 microseconds
004F 30B3F8           60         JNB   _clock, InhibitLoop ;Check again for inhibit
0052 20B402           61         JB    _data,  EnSend      ;Check for request-to-send
0055 C3               62         CLR   C
0056 22               63         RET
0057                  64     EnSend:
                      65         ;Output Start bit (0)
0057 C3               66         CLR   C
0058 1171             67         ACALL BitOut
                      68         ;Output Keycode
005A                  69     ByteOutLoop:
005A 13               70         RRC   A
005B 1171             71         ACALL BitOut
005D DFFB             72         DJNZ  R7,     ByteOutLoop
                      73         ;Output Parity bit (odd parity)
005F A200             74         MOV   C,      _parity
0061 1171             75         ACALL BitOut
                      76         ;Output Stop bit (1)
0063 D3               77         SETB  C
0064 92B4             78         MOV   _data,  C
0066 1196             79         ACALL Delay20us
0068 C2B3             80         CLR   _clock
006A 117E             81         ACALL Delay370us
006C D2B4             82         SETB  _data       ;data=1
006E D2B3             83         SETB  _clock      ;clock=1
0070 22               84         RET
                      85     
0071                  86     BitOut:
0071 92B4             87         MOV   _data,  C
0073 1196             88         ACALL Delay20us
0075 C2B3             89         CLR   _clock
0077 1191             90         ACALL Delay40us
0079 D2B3             91         SETB  _clock
007B 1196             92         ACALL Delay20us
007D 22               93         RET
                      94     
007E                  95     Delay370us:
007E 118F             96         ACALL Delay50us
0080 118F             97         ACALL Delay50us
0082 118F             98         ACALL Delay50us
0084 118F             99         ACALL Delay50us
0086 118F            100         ACALL Delay50us
0088 118F            101         ACALL Delay50us
008A 118F            102         ACALL Delay50us
008C 1196            103         ACALL Delay20us
008E 22              104         RET
                     105     
008F                 106     Delay50us:
008F 119B            107         ACALL Delay10us
0091                 108     Delay40us:
0091 1196            109         ACALL Delay20us
0093 1196            110         ACALL Delay20us
0095 22              111         RET
                     112     
0096                 113     Delay20us:
0096 119B            114         ACALL Delay10us
0098 119B            115         ACALL Delay10us
009A 22              116         RET
                     117     
009B                 118     Delay10us:
009B 00              119         NOP
009C 00              120         NOP
009D 22              121         RET
                     122     
                     123         END
A51 MACRO ASSEMBLER  PS2                                                                  10/27/2008 11:52:56 PAGE     3

SYMBOL TABLE LISTING
------ ----- -------


N A M E             T Y P E  V A L U E   ATTRIBUTES

BITOUT . . . . . .  C ADDR   0071H   A   
BYTEOUTLOOP. . . .  C ADDR   005AH   A   
CODEOUT. . . . . .  C ADDR   0048H   A   
DE . . . . . . . .  C ADDR   003EH   A   
DE1. . . . . . . .  C ADDR   0019H   A   
DEL. . . . . . . .  C ADDR   003CH   A   
DELAY10US. . . . .  C ADDR   009BH   A   
DELAY20US. . . . .  C ADDR   0096H   A   
DELAY370US . . . .  C ADDR   007EH   A   
DELAY40US. . . . .  C ADDR   0091H   A   
DELAY50US. . . . .  C ADDR   008FH   A   
ENSEND . . . . . .  C ADDR   0057H   A   
INHIBITLOOP. . . .  C ADDR   004AH   A   
LOOP . . . . . . .  C ADDR   0005H   A   
MAIN . . . . . . .  C ADDR   0002H   A   
P. . . . . . . . .  B ADDR   00D0H.0 A   
P3 . . . . . . . .  D ADDR   00B0H   A   
SP . . . . . . . .  D ADDR   0081H   A   
_CLOCK . . . . . .  B ADDR   00B0H.3 A   
_DATA. . . . . . .  B ADDR   00B0H.4 A   
_PARITY. . . . . .  B ADDR   0020H.0 A   


REGISTER BANK(S) USED: 0 

ASSEMBLY COMPLETE.  0 WARNING(S), 0 ERROR(S)

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