plltb.vhd

实现同步时采用锁相环

--///////////////////////////////////////////////////////////////////////////
--///////////////////////////////////////////////////////////////////////////
--/
--/ File        : pllTb.vhd
--/ Author	: ParthusCeva Inc.
--// Date	: Mon Feb 17 06:08:33 2003
--// Info	: Job No = 12364215
--/_______________________________________________________________________
--/ 
--/        Copyright (c) ParthusCeva Inc.
--/ 
--/ This code is confidential and proprietary product of ParthusCeva. Any
--/ unauthorized use, reproduction or transfer of this code is strictly
--/ prohibited.
--/_______________________________________________________________________
--/ 
--/		 
--/_______________________________________________________________________
--/ 
--/
--///////////////////////////////////////////////////////////////////////////
--///////////////////////////////////////////////////////////////////////////

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity tb_pllxpert is

end tb_pllxpert;

architecture beh of tb_pllxpert is

component xtop4215
	port (
		refClk		: in  std_logic;
		porL		: in  std_logic;
		sleepL		: in  std_logic;
		forceBypass	: in  std_logic;
		FBD0		: in  std_logic;
		FBD1		: in  std_logic;
		FBD2		: in  std_logic;
		FBD3		: in  std_logic;
		FBD4		: in  std_logic;
		FBD5		: in  std_logic;
		FBD6		: in  std_logic;
		FBD7		: in  std_logic;
		IPD0		: in  std_logic;
		IPD1		: in  std_logic;
		IPD2		: in  std_logic;
		IPD3		: in  std_logic;
		IPD4		: in  std_logic;
		IPD5		: in  std_logic;
		IPD6		: in  std_logic;
		IPD7		: in  std_logic;
		xClk01		: out  std_logic;
		xClk02		: out  std_logic;
		xClk03		: out  std_logic;
		pllLock		: out std_logic;
		sysResetL	: out std_logic);
end component;


signal porL        : std_logic;
signal refClk      : std_logic := '0';
signal sleepL      : std_logic;
signal forceBypass : std_logic;

signal FBD : std_logic_vector(7 downto 0) := "00111111"; -- 63 => div by 64
signal IPD		: std_logic_vector(7 downto 0) := "00000000"; -- 0 => div by 1


signal xClk01		: std_logic;
signal xClk02		: std_logic;
signal xClk03		: std_logic;

signal pllLock     : std_logic;
signal sysResetL   : std_logic;

signal half_refClk_period	: time := 111111 ps;


procedure doResetL(signal porL : out std_logic) is
	begin  -- doResetL
	porL <= '0';
	wait for 1000 ns;
	porL <= '1';
	end doResetL;

procedure doSleepL(signal sleepL : out std_logic) is
	begin  -- doSleepL
	sleepL <= '0';
	wait for 1000 ns;
	sleepL <= '1';
	end doSleepL;
	begin  -- beh

Ixtop4215 : xtop4215
	port map (
		refClk		=> refClk,
		porL		=> porL,
		sleepL		=> sleepL,
		forceBypass	=> forceBypass,
		FBD0 => FBD(0),
		FBD1 => FBD(1),
		FBD2 => FBD(2),
		FBD3 => FBD(3),
		FBD4 => FBD(4),
		FBD5 => FBD(5),
		FBD6 => FBD(6),
		FBD7 => FBD(7),
		IPD0 => IPD(0),
		IPD1 => IPD(1),
		IPD2 => IPD(2),
		IPD3 => IPD(3),
		IPD4 => IPD(4),
		IPD5 => IPD(5),
		IPD6 => IPD(6),
		IPD7 => IPD(7),
		xClk01 => xClk01,
		xClk02 => xClk02,
		xClk03 => xClk03,
		pllLock		=> pllLock,
		sysResetL	=> sysResetL);


	process
		begin  -- process
		wait for half_refClk_period;
		refClk <= not refClk;
	end process;

	process
		begin  -- process
		sleepL <= '1';
		porL <= '0';
		forceBypass <= '0';

		doResetL(porL);
		assert false report "Initial Reset Complete" severity note;

		wait for 46000.000000 ns;
		doSleepL(sleepL);
		assert false report "Taken out of sleep mode" severity note;

		wait for 34500.000000 ns;
		FBD <= CONV_STD_LOGIC_VECTOR(36, 8);
		half_refClk_period <= 85.535882 ns;
		assert false report "Set FBD" severity note;

		wait for 5750.000000 ns;
		doResetL(porL);
		assert false report "Reset in order to resume correct operation" severity note;

		wait for 34500.000000 ns;
		FBD <= CONV_STD_LOGIC_VECTOR(113, 8);
		half_refClk_period <= 158.503725 ns;
		assert false report "Set FBD" severity note;

		wait for 5750.000000 ns;
		doResetL(porL);
		assert false report "Reset in order to resume correct operation" severity note;

		wait for 34500.000000 ns;
		FBD <= CONV_STD_LOGIC_VECTOR(255, 8);

		wait for 5750.000000 ns;
		doResetL(porL);
		assert false report "Set FBD. This is an invalid selection" severity note;
		half_refClk_period <= 111.111111 ns;

		wait for 5750.000000 ns;
		FBD <= CONV_STD_LOGIC_VECTOR(63, 8);

		wait for 5750.000000 ns;
		doResetL(porL);
		assert false report "Reset in order to resume correct operation" severity note;

		wait for 5750.000000 ns;
		forceBypass <= '1';
		doResetL(porL);
		assert false report "Going into byPass mode" severity note;

		wait;
	end process;

end beh;