barrel_shifter_32.v

this module performs the task of a barrel-shifter 16 or 32 bits

//**********************************************************************************
//   Copyright (c) 2007 by WichipTech
//   All right reserved.
//
//   Copyright Notification
//   No part may be reproduced except as authorized by written permission.
//
//   TITLE  : Barrel shifter 32 bits
//   FILE   : barrel_shifter_32.v
//   Author : Tran, Minh-Cuong
//   E-mail : [e-mail]
//   Tel    : [phone]
//   Fax    :
//   DESCRIPTION:  Barrel shifter
//
//
//   ORGANIZATION: WiCHIP Technologies, Inc.
//                 106 - C5 - Thanh Xuan Bac
//                 HaNoi, VIETNAM
// *********************************************************************************


module	barrel_shifter_32(
			input_code,
			output_code,
			shift
		);

//**********************************************************************************
//         Input ports
//**********************************************************************************
input	[31:0]	input_code;		 	//input code
input	[4:0]	shift;				//number of bits to shift

//**********************************************************************************
//         Output ports
//**********************************************************************************
output	[31:0]	output_code;		//output code

//**********************************************************************************
//         Signal declaration: reg
//**********************************************************************************

//**********************************************************************************
//         Signal declaration: wire
//**********************************************************************************
wire	[31:0]	shift_0;
wire	[31:0]	shift_1;
wire	[31:0]	shift_2;
wire	[31:0]	shift_3;

assign	shift_0[30: 0] = shift[0] ? input_code[31: 1] : input_code[30: 0];
assign	shift_0[31   ] = shift[0] ? 1'b0 			  : input_code[31   ];

assign	shift_1[29: 0] = shift[1] ? shift_0[31: 2] : shift_0[29: 0];
assign	shift_1[31:30] = shift[1] ? 2'b00		   : shift_0[31:30];

assign	shift_2[27: 0] = shift[2] ? shift_1[31: 4] : shift_1[27: 0];
assign	shift_2[31:28] = shift[2] ? 4'b0000		   : shift_1[31:28];

assign	shift_3[23: 0] = shift[3] ? shift_2[31: 8] : shift_2[23: 0];
assign	shift_3[31:24] = shift[3] ? 8'b00000000	   : shift_2[31:24];

assign	output_code[15: 0] = shift[4] ? shift_3[31: 16] 		: shift_3[15: 0];
assign	output_code[31:16] = shift[4] ? 16'b0000000000000000	: shift_3[31:16];



endmodule