pcisets.c

open source bios with linux platform, very good and can be reused.

	pci_write(CURRENT, 0x4e, pci_dummy[0]);
	pci_write(CURRENT, 0xe3, pci_dummy[1]);
}

/* AMD 760/756/751 & VIA (M)VP3  */

static void amd7xx_activate(void)
{
	pci_dummy[0]=pci_read(CURRENT, 0x40); /* IO Control 1 */
	pci_dummy[1]=pci_read(CURRENT, 0x43); /* SEGEN */
	
	pci_write(CURRENT, 0x40, pci_dummy[0] | 0x01);
	pci_write(CURRENT, 0x43, pci_dummy[1] | 0x80);
}

static void amd7xx_deactivate(void)
{
	pci_write(CURRENT, 0x43, pci_dummy[1]);
	pci_write(CURRENT, 0x40, pci_dummy[0]);
}

static void viamvp3_activate(void)
{
	hostbridge = pci_find_class(PCI_CLASS_BRIDGE_HOST<<8,NULL);
	if (!hostbridge)
		return;
	pci_dummy[0]=pci_read(hostbridge,0x52);
	pci_write(hostbridge, 0x52, pci_dummy[0] & 0xcf);
	pci_dummy[1]=pci_read(hostbridge, 0x63);
	pci_write(hostbridge, 0x63, pci_dummy[1] & 0x0f);
	pci_dummy[2]=pci_read(CURRENT,0x43);
	pci_write(CURRENT, 0x43, pci_dummy[2] |0xF8);

	pci_write(CURRENT, 0x40, pci_read(CURRENT,0x40) | 0x01);
}

static void viamvp3_deactivate(void)
{
	if (!hostbridge)
		return;
	pci_write(CURRENT, 0x40, pci_read(CURRENT,0x40) & 0xfe);
	pci_write(hostbridge, 0x63, pci_dummy[1]);
	pci_write(hostbridge, 0x52, pci_dummy[0]);
	pci_write(CURRENT, 0x43, pci_dummy[2]);
}

/* SiS works with 530/5595 chipsets */

static void sis_activate(void) 
{
	char b;
	hostbridge = pci_find_class(PCI_CLASS_BRIDGE_HOST<<8,NULL);
	if (!hostbridge)
		return;
	
	pci_dummy[0]=pci_read(hostbridge, 0x76);
	pci_dummy[1]=readb(0x51);
	pci_dummy[2]=pci_read(CURRENT, 0x40);
	pci_dummy[3]=pci_read(CURRENT, 0x45);
	
	/* disable shadow */
	pci_write(hostbridge, 0x76, 0x00);
	/* disable cache */
	writeb(pci_dummy[1] & 0x7f, 0x51);
	
	/* Enable 0xFFF8000~0xFFFF0000 decoding on SiS 540/630 */
	pci_write(CURRENT, 0x40, pci_dummy[2]|0x0b);
	/* Flash write enable on SiS 540/630 */
	pci_write(CURRENT, 0x45, pci_dummy[3]|0x40);

	/* The same thing on SiS 950 SuperIO side */
	outb(0x87, 0x2e);
	outb(0x01, 0x2e);
	outb(0x55, 0x2e);
	outb(0x55, 0x2e);
	if (inb(0x2f) != 0x87) {
		/* printf("Can not access SiS 950\n"); */
		return;
	}
	
	outb(0x24, 0x2e);
	b = inb(0x2f) | 0xfc;
	outb(0x24, 0x2e);
	outb(b, 0x2f);
	outb(0x02, 0x2e);
	outb(0x02, 0x2f);
}

static void sis_deactivate(void) 
{
	if (!hostbridge)
		return;

	/* Restore PCI Registers */
	pci_write(hostbridge, 0x76, pci_dummy[0]);
	pci_write(CURRENT, 0x45, pci_dummy[2]);
	pci_write(CURRENT, 0x45, pci_dummy[3]);
	/* restore cache to original status */
	writeb(pci_dummy[1], 0x51);
}

/* UMC 486 Chipset 8881/886a */

static void umc_activate(void)
{
	hostbridge = pci_find_class(PCI_CLASS_BRIDGE_HOST<<8,NULL);
	if (!hostbridge)
		return;
	
        pci_dummy[0]=pci_read(hostbridge, 0x54);
	pci_dummy[1]=pci_read(hostbridge, 0x55);

        pci_write(hostbridge, 0x54, 0x00);
        pci_write(hostbridge, 0x55, 0x40);

	pci_write(CURRENT,0x47, pci_read(CURRENT,0x47) & ~0x40);
}

static void umc_deactivate(void)
{
	if (!hostbridge)
		return;
	
	pci_write(CURRENT, 0x47, pci_read(CURRENT,0x47) | 0x40);

        pci_write(hostbridge, 0x54, pci_dummy[0]);
        pci_write(hostbridge, 0x55, pci_dummy[1]);
}

/* CS5530 functions */

static void cs5530_activate(void)
{
	/* Save modified registers for later reset */
	pci_dummy[0]=pci_read(CURRENT,0x52);
	pci_dummy[1]=pci_read(CURRENT,0x5b);

	/* enable rom write access */
	pci_write(CURRENT, 0x52, pci_dummy[0]|0x06);

	/* enable rom positive decode */
	// pci_write(CURRENT,0x5b, pci_dummy[1]|0x20);
	// pci_write(CURRENT,0x52, pci_read(CURRENT,0x52)|0x01);
}

static void cs5530_deactivate(void)
{
        pci_write(CURRENT, 0x52, pci_dummy[0]);
        // pci_write(CURRENT, 0x5b, pci_dummy[1]);
}

/* Reliance / ServerWorks */

static void reliance_activate(void)
{
	pci_dummy[0]=pci_read(CURRENT,0x41);
	pci_dummy[1]=pci_read(CURRENT,0x70);
	pci_dummy[2]=inb(0xc6f);
	
	/* Enable 512k */
	pci_write(CURRENT, 0x41, pci_dummy[0] | 0x02);
	/* Enable 4MB */
	pci_write(CURRENT, 0x70, pci_dummy[1] | 0x80);
	/* Enable flash write */
	outb(pci_dummy[2] | 0x40, 0xc6f);
}
 
static void reliance_deactivate(void)
{
	pci_write(CURRENT, 0x41, pci_dummy[0]);
	pci_write(CURRENT, 0x70, pci_dummy[1]);
	outb(pci_dummy[2], 0xc6f);
}

/* ALi Methods - untested */
static void ali_activate(void)
{
	pci_dummy[0]=pci_read(CURRENT, 0x47);
	pci_dummy[1]=pci_read(CURRENT, 0x79);
	pci_dummy[2]=pci_read(CURRENT, 0x7f);

	/* write enable, 256k enable */
#ifdef OLD_ALi
	pci_write(CURRENT, 0x47, pci_dummy[0]|0x47);
#else
	pci_write(CURRENT, 0x47, pci_dummy[0]|0x43);
#endif

	/* M1543C rev B1 supports 512k. Register reserved before */
#ifdef OLD_ALi
	pci_write(CURRENT, 0x79, pci_dummy[1]|0x10);
	pci_write(CURRENT, 0x7f, pci_dummy[2]|0x01);
#else
	pci_write(CURRENT, 0x7b, pci_dummy[1]|0x10);
#endif
}

static void ali_deactivate(void)
{
	pci_write(CURRENT, 0x47, pci_dummy[0]);
	pci_write(CURRENT, 0x79, pci_dummy[1]);
	pci_write(CURRENT, 0x7f, pci_dummy[2]);
}

/* Default routines. Use these if nothing else works */
#if 0
static unsigned int def_addr;
#endif
static void default_activate(void)
{
#if 0 && LINUX_VERSION_CODE > KERNEL_VERSION(2,4,0)
	struct resource *r;
	
	r=&CURRENT->resource[PCI_ROM_RESOURCE];

	r->flags |= PCI_ROM_ADDRESS_ENABLE;
	r->flags &= ~(IORESOURCE_READONLY|IORESOURCE_CACHEABLE);
	pci_read_config_dword(CURRENT, CURRENT->rom_base_reg, &def_addr);
	if (def_addr)
		pci_write_config_dword (CURRENT, CURRENT->rom_base_reg,
				def_addr|PCI_ROM_ADDRESS_ENABLE);
#endif
#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,0)
	long ret;

	if (pci_enable_device(CURRENT))
		return;

	pci_write_config_dword (CURRENT, CURRENT->rom_base_reg,
			pci_resource_start(CURRENT, PCI_ROM_RESOURCE)|
			PCI_ROM_ADDRESS_ENABLE);

	ret=(long)request_mem_region( pci_resource_start(CURRENT, 
				PCI_ROM_RESOURCE), pci_resource_len(CURRENT,
					PCI_ROM_RESOURCE), "Firmware memory");
	if (!ret)
		printk (KERN_ERR "BIOS:   cannot reserve MMROM region " 
				"0x%lx+0x%lx\n",
				pci_resource_start(CURRENT, PCI_ROM_RESOURCE),
				pci_resource_len(CURRENT, PCI_ROM_RESOURCE));
	else
		printk (KERN_INFO "BIOS:   mapped rom region to 0x%lx\n", ret);
#endif
}

static void default_deactivate(void)
{
#if 0 && LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,0)
	struct resource *r;
	r=&CURRENT->resource[PCI_ROM_RESOURCE];
	r->flags &= ~PCI_ROM_ADDRESS_ENABLE;
	r->flags |= (IORESOURCE_READONLY|IORESOURCE_CACHEABLE);
	pci_write_config_dword (CURRENT, CURRENT->rom_base_reg, def_addr);
#endif
#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,0)
	release_mem_region(pci_resource_start(CURRENT, PCI_ROM_RESOURCE),
			pci_resource_len(CURRENT, PCI_ROM_RESOURCE));
#endif
}

const struct flashdev devices[] = {
	/* Intel 4x0 chipsets */
	{ (int[]) { 0x8086122e, 0x80861234, 0x80867000, 0x80867110, 
		    0x80867198, 0 },
	  intel4x0_activate, intel4x0_deactivate, system_memarea },

	/* Intel 8x0 chipsets */	
	{ (int[]) { 0x80862410, 0x80862420, 0x80862440, 0x8086244c,
	            0x80862480, 0x8086248c, 0x80867600, 0 },
	  intel8x0_activate, intel8x0_deactivate, system_memarea },

	/* Irongate 75x, AMD-76xMP(X), VT8231/3 */
	{ (int[]) { 0x10227400, 0x10227408, 0x10227410, 0x10227440,
		    0x11068231, 0x11063074, 0 },
	  amd7xx_activate, amd7xx_deactivate, system_memarea },

	/* AMD Hammer (thor chipset) */
	{ (int[]) { 0x10227468, 0 },
	  amd7xx_activate, amd7xx_deactivate, system_memarea },

	/* VIA (M)VP3, VT82C686 [Apollo Super South] */
	{ (int[]) { 0x11060586, 0x11060596, 0x11060686, 0 },
	  viamvp3_activate, viamvp3_deactivate, memarea_256k },
	  
	/* UMC */  
	{ (int[]) { 0x1060886a, 0x10600886, 0x1060e886, 0x10608886, 0 },
	   umc_activate, umc_deactivate, system_memarea },

	/* SiS */
	{ (int[]) { 0x10390008, 0x10390018, 0 },
	   sis_activate, sis_deactivate, system_memarea },

	/* OPTi */
	{ (int[]) { 0x1045c558, 0 },
	  default_activate, default_deactivate, system_memarea },

	/* NSC CS5530(A) */
	{ (int[]) { 0x10780100, 0 },
	  cs5530_activate, cs5530_deactivate, memarea_256k },

	/* Reliance/ServerWorks NB6xxx */
	{ (int[]) { 0x11660200, 0 },
	  reliance_activate, reliance_deactivate, system_memarea },

	/* ALi */
	{ (int[]) { 0x10b91523, 0x10b91533, 0x10b91543, 0 },
	  ali_activate, ali_deactivate, system_memarea },

	{ (int[]) { 0x00000000 },
	  default_activate, default_deactivate, default_memarea }
};

#endif /* CONFIG_PCI */