t8422_ob.c

F2833x / F2823x C/C++ Header Files and Peripheral Examples.It is very useful.

 *      Initializes the handle passed into the function
 *    - Pre-initializes the following DMA channel registers:
 *      - DMACICR with the value defined in the header file
 *      - DNASSAL/AU with the McBSP receive register address
 *      - DMACFN to one
 *    - Calculates the value for the DMACCR and returns it in
 *      the memory location where *pCcr is pointing to
 *
 * Parameters:
 *    - DMA_Handle *hDma: Pointer to the handle of the DMA
 *    - MCBSP_Handle hMcbSP: Handle to the McBSP port
 *    - int iIrq: The interrupt number associated with the
 *      serial port used
 *    - int iChannelNumber: Which DMA channel to use
 *    - unsigned int *pCcr: Pointer to the DMACCR value in the
 *      data converter object (pass-in return value
 * Return value (of type TTIDCSTATUS):
 *    - TIDC_NO_ERR in case everything was OK
 *    - TIDC_ERR_DMA if the DMA channel could not be opened
 *
 * Globals modified: Inside the data converter object:
 *    - hDma
 *    - uiCcrValue
 *
 * Resources used:
 *    - One DMA channel
*/
/****************************************************************/
static TTIDCSTATUS InitDma(DMA_Handle *hDma,
                           unsigned long ulAdcAddress,
                           unsigned int uiIrq,
                           unsigned int iChannelNumber,
                           unsigned int *pCcr)
{
    DMA_Config cfgDma;                /* defined in the CSL     */
    unsigned int uiEventId;

    *hDma = DMA_open(iChannelNumber, 0);
    if (*hDma == INV)
        return TIDC_ERR_DMA;

    /* set the default values of the channel registers          */
    memset(&cfgDma, 0x0000, sizeof(cfgDma));

    /* DMACCR (channel control register) setup                  */
    /* First, select the synchronization event; as they are not */
    /* linear, they cannot be used directly.                    */
    /* The macros of the events are based on the event ID's from*/
    /* the chip support library                                 */
    switch (uiIrq)
    {
        case IRQ_EVT_INT0:  uiEventId = 15; /* IRQ_EVT_INT0 = 2 */
                            break;
        case IRQ_EVT_INT1:  uiEventId = 16; /* IRQ_EVT_INT1 = 16*/
                            break;
        case IRQ_EVT_INT2:  uiEventId = 17; /* IRQ_EVT_INT2 = 3 */
                            break;
        case IRQ_EVT_INT3:  uiEventId = 18; /* IRQ_EVT_INT3 = 11*/
                            break;
        case IRQ_EVT_INT4:  uiEventId = 19; /* IRQ_EVT_INT4 = 19*/
                            break;          /* only C5509/C5510 */
        case IRQ_EVT_INT5:  uiEventId = 20; /* IRQ_EVT_INT5 = 23*/
                            break;          /* only C5510       */
        default:            return TIDC_ERR_BADARGS;
    }

    /* now create the correct settings for the DMACCR register  */
    /* they will be written to the DMA channel during readblock */
    *pCcr = ADS8422_DMACCR_VALUE | uiEventId;

    /* DMACICR (channel interrupt control) setup                */
    cfgDma.dmacicr = ADS8422_DMACICR_VALUE;

    /* DMACSSAL/AU (channel source start address low/high) setup*/
    /* type DMA_AdrPtr is defined in the CSL                    */
    ulAdcAddress = ulAdcAddress << 1;
    cfgDma.dmacssal = (DMA_AdrPtr)ulAdcAddress;
    cfgDma.dmacssau = (Uint16)(ulAdcAddress >> 16);

    /* DMACEN (channel element number) setup                    */
    cfgDma.dmacen = 0;

    /* DMACFN (channel frame number) setup                      */
    cfgDma.dmacfn = 1; /* we will only transfer a single frame  */

    /* Now that all registers are set-up, to the actual         */
    /* configuration of the DMA channel                         */
    DMA_config(*hDma, &cfgDma);

    return TIDC_NO_ERR;
}


/****************************************************************/
/* InitEmif()                                                   */
/**Operation:
 *     - Sets up the EMIF to the correct timings for the ADS8422
 *
 * Parameters:
 *     - unsigned int *pAddress: Address of the ADS8422
 *
 * Return value: Of type TTIDCSTATUS:
 *     - TIDC_NO_ERR: Everything was OK
 *
 * Globals modified:
 *     - None
 *
 * Resources used:
 *     - None
 */
/****************************************************************/
static TTIDCSTATUS InitEmif(volatile unsigned int *pAddress)
{
    int iCeValue;
    unsigned int uiCeSpace;

    iCeValue = ADS8422_RD_HOLD
                | (ADS8422_RD_STROBE << 2)
                | (ADS8422_RD_SETUP << 8)
                | (ADS8422_MTYPE << 12);

    uiCeSpace = (unsigned int)(((unsigned long)pAddress >> 21)
                                               & 0x00000003);

    /* get the address space for the control register           */
    switch (uiCeSpace)
    {
        case 0: EMIF_RSET(CE01, iCeValue);
                break;
        case 1: EMIF_RSET(CE11, iCeValue);
                break;
        case 2: EMIF_RSET(CE21, iCeValue);
                break;
        case 3: EMIF_RSET(CE31, iCeValue);
                break;
    }

    return TIDC_NO_ERR;
}


/****************************************************************/
/* SubmitBlock()                                                */
/** Operation:
 *    - The following operations are performed depending on if
 *      there is already a transfer running or not.
 *     - If this is the first transfer, it starts a dummy
 *       transfer to clear synchronization events, which are
 *       eventually pending and sets the autoinit mode of the
 *       DMA and initalizes the DMA registers.
 *     - If this is the second transfer, it initializes the
 *       destination and count registers and sets the ENDPROG
 *       bit to one
 *
 * Parameters:
 *     - DMA_Handle hDma: This is the handle to the DMA channel
 *     - TADS8422BUFOBJ bufObj: Pointer to the transfer object
 *       which holds the parameters for the transfer
 *     - unsigned int uiCcr: The value for the DMA channel
 *       control register as calculated during ADS8422_initDma.
 *     - int iIndex: Is 1, if this is the first transfer and
 *       2 if this is the second submitted transfer
 *
 * Return value (of type TTIDCSTATUS):
 *     - TIDC_NO_ERR: No error occurred
 *
 * Globals modified: in DC object:
 *     - None
 *
 * Resources used:
 *     - None
*/
/****************************************************************/
static TTIDCSTATUS SubmitBlock(DMA_Handle hDma,
                               TADS8422BUFOBJ bufObj,
                               unsigned int uiCcr,
                               int iIndex)
{
    unsigned int uiDstPort;
    unsigned long ulDst;

    /* the DMA controller needs byte addresses                  */
    ulDst = (unsigned long)(bufObj.uiBufPtr) << 1;

    /* decide, in which memory area the buffer is located       */
    uiDstPort = ADS8422_DMACSDP_EMIF_DST;
    if (ulDst <= DCP_DARAM_END)
        uiDstPort = ADS8422_DMACSDP_DARAM_DST;
    if (ulDst >= DCP_SARAM_START && ulDst <= DCP_SARAM_END)
        uiDstPort = ADS8422_DMACSDP_SARAM_DST;

    /* wait until the channel is ready to program               */
    while ((DMA_RGETH(hDma, DMACCR) & ADS8422_DMA_ENDPROG) != 0);

    /* if it is the first transfer, submit the dummy transfer   */
    /* and set the AUTOINIT bit                                 */
    if (iIndex == 1)
    {
        (void)SubmitDummyXfer(hDma);
        DMA_FSETH(hDma, DMACCR, AUTOINIT, 1);
    }

    /* set the DMA Channel Source & Destination Parameter reg.  */
    DMA_RSETH(hDma,
              DMACSDP,
              ADS8422_DMACSDP_VALUE | uiDstPort);

    /* set the DMA Channel Element Number Register (DMACEN)     */
    DMA_RSETH(hDma, DMACEN, bufObj.uiBufSize);

    /* set the DMA Channel Destination Start Address register   */
    DMA_RSETH(hDma, DMACDSAL,  (unsigned int)ulDst);
    DMA_RSETH(hDma, DMACDSAU, ((unsigned int)(ulDst >> 16)));

    /* set the DMA Channel Control Register (DMACCR)            */
    /* if it is the first transfer, program the DMACCR and set  */
    /* the ENABLE bit to one, but leave the ENDPROG bit set to 0*/
    if (iIndex == 1)
    {
        DMA_RSETH(hDma, DMACCR, uiCcr);
        DMA_FSETH(hDma, DMACCR, EN, 1);
    }
    /* if it is the second transfer, set the ENBALE bit to 1    */
    /* and the ENDPORG bit to 1                                 */
    else
    {
        DMA_FSETH(hDma, DMACCR, EN, 1);
        DMA_FSETH(hDma, DMACCR, ENDPROG, 1);
    }

    return TIDC_NO_ERR;
}


/****************************************************************/
/* SubmitDummyXfer()                                            */
/** Operation:
 *     - Starts a dummy transfer without synchronization
 *     - Waits for the transfer to complete
 *     - Clears the control status register
 *     - Clears the channel control register
 *
 * Parameters:
 *     - DMA_Handle hDma: This is the handle to the DMA channel
 *
 * Return value (of type TTIDCSTATUS):
 *     - TIDC_NO_ERR: No error occurred
 *
 * Globals modified:
 *     - None
 *
 * Resources used:
 *     - None
*/
/****************************************************************/
static TTIDCSTATUS SubmitDummyXfer(DMA_Handle hDma)
{
    unsigned int uiDstPort;
    unsigned long ulDst;
    unsigned int uiDummy;

    /* the DMA controller needs byte addresses                  */
    ulDst = ((unsigned long)&uiDummy) << 1;

    /* decide, in which memory area the buffer is located       */
    uiDstPort = ADS8422_DMACSDP_EMIF_DST;

    /* is the address in DARAM?                                 */
    if (ulDst <= DCP_DARAM_END)
        uiDstPort = ADS8422_DMACSDP_DARAM_DST;

    /* is the address in SARAM?                                 */
    else if (ulDst <= DCP_SARAM_END)
        uiDstPort = ADS8422_DMACSDP_SARAM_DST;

    /* set the DMA Channel Source & Destination Parameter reg.  */
    DMA_RSETH(hDma,
              DMACSDP,
              ADS8422_DMACSDP_VALUE | uiDstPort);

    /* set the DMA Channel Element Number register (DMACEN)     */
    DMA_RSETH(hDma, DMACEN, 1);

    /* set the DMA Channel Destination Start Address register   */
    DMA_RSETH(hDma, DMACDSAL,  (unsigned int)ulDst);
    DMA_RSETH(hDma, DMACDSAU, ((unsigned int)(ulDst >> 16)));

    /* set the Dma Channel Control Register (DMACCR)            */
    DMA_RSETH(hDma, DMACCR, ADS8422_DMACCR_VALUE_DUMMY);

    /* wait for the dummy transfer to finish                    */
    while (DMA_FGETH(hDma, DMACSR, BLOCK) != 1);

    DMA_RGETH(hDma, DMACSR); /* clear event */
    DMA_RSETH(hDma, DMACCR, 0); /* clear CCR */

    IRQ_clear(DMA_getEventId(hDma)); /* clear int flag */

   return TIDC_NO_ERR;
}

/****************************************************************/
/* END OF t8422_ob.c                                             */
/****************************************************************/
/*TIDC_Wizard Auto Code End}}*/