cam2tft.c

This is the source code of Camera driver for OV2640 camera from OmniVision using in Blackfin platfor

	CAM_write_reg(0x8635);  // CTRL2
	CAM_write_reg(0x5000);  // CTRL1

	CAM_write_reg(0x5190);  // H_SIZE
	CAM_write_reg(0x5218);  // V_SIZE

	CAM_write_reg(0x5300);  // OFFSET_X
	CAM_write_reg(0x5400);  // OFFSET_Y
	CAM_write_reg(0x5588);  // H_SIZE, V_SIZE, OFFSET_X, OFFSET_Y
	CAM_write_reg(0x5700);  // H_SIZE

	CAM_write_reg(0x5A90);  // OUTW
	CAM_write_reg(0x5B18);  // OUTH
	CAM_write_reg(0x5C05);  // OUTH, OUTW
	CAM_write_reg(0xD382);  // DVP speed control

	CAM_write_reg(0xE51F);  // reserved
	CAM_write_reg(0xE167);  // reserved
	CAM_write_reg(0xE000);  // RESET
	CAM_write_reg(0xDD7F);  // reserved
	CAM_write_reg(0x0500);  // use DSP

	CAM_write_reg(0x8750);  // !Black & White Pixel Canceling

	CAM_write_reg(0xC381); // CTRL1: CIP, PRE
	CAM_write_reg(0xC201); // CTRL0: RAW_EN
//	CAM_write_reg(0xC301); // CTRL1: CIP, PRE
//	CAM_write_reg(0xC281); // CTRL0: RAW_EN
	CAM_write_reg(0x9201); // reserved
	CAM_write_reg(0x9300); // reserved
	CAM_write_reg(0x9200); // reserved
	CAM_write_reg(0x9300); // reserved
}

void CAM_raw_EC(void){
	CAM_write_reg(0xFF01);
	CAM_write_reg(0x042B); // Maximum Exposure
	CAM_write_reg(0x10FF); // Maximum Exposure
	CAM_write_reg(0x453F); // Maximum Exposure
//	CAM_write_reg(0x1180); // Double clock rate
	CAM_write_reg(0x0000); // AGC = 0
	CAM_write_reg(0xFF00);
	CAM_write_reg(0xC383); // Use LENC
}

void CAM_init(void){
	CAM_write_reg(0xff00);
	CAM_write_reg(0x2cff);
	CAM_write_reg(0x2edf);
	CAM_write_reg(0xff01);
	CAM_write_reg(0x3c32);
	CAM_write_reg(0x1100);
	CAM_write_reg(0x0902);
	CAM_write_reg(0x0428);
	CAM_write_reg(0x13e5);
	CAM_write_reg(0x1448);
	CAM_write_reg(0x2c0c);
	CAM_write_reg(0x3378);
	CAM_write_reg(0x3a33);
	CAM_write_reg(0x3bfb);
	CAM_write_reg(0x3e00);
	CAM_write_reg(0x4311);
	CAM_write_reg(0x1610);
	CAM_write_reg(0x3902);
	CAM_write_reg(0x3588);
	CAM_write_reg(0x220a);
	CAM_write_reg(0x3740);
	CAM_write_reg(0x2300);
	CAM_write_reg(0x34a0);
	CAM_write_reg(0x361a);
	CAM_write_reg(0x0602);
	CAM_write_reg(0x07c0);
	CAM_write_reg(0x0db7);
	CAM_write_reg(0x0e01);
	CAM_write_reg(0x4c00);
	CAM_write_reg(0x4a81);
	CAM_write_reg(0x2199);
	CAM_write_reg(0x243a);
	CAM_write_reg(0x2532);
	CAM_write_reg(0x2682);
	CAM_write_reg(0x5c00);
	CAM_write_reg(0x6300);
	CAM_write_reg(0x5d55);
	CAM_write_reg(0x5e7d);
	CAM_write_reg(0x5f7d);
	CAM_write_reg(0x6055);
	CAM_write_reg(0x6170);
	CAM_write_reg(0x6280);
	CAM_write_reg(0x7c05);
	CAM_write_reg(0x2080);
	CAM_write_reg(0x2830);
	CAM_write_reg(0x6c00);
	CAM_write_reg(0x6d80);
	CAM_write_reg(0x6e00);
	CAM_write_reg(0x7002);
	CAM_write_reg(0x7194);
	CAM_write_reg(0x73c1);
	CAM_write_reg(0x3d34);
	CAM_write_reg(0x5a57);
	CAM_write_reg(0x4fbb);
	CAM_write_reg(0x509c);
	CAM_write_reg(0xff00);
	CAM_write_reg(0xe57f);
	CAM_write_reg(0xf9c0);
	CAM_write_reg(0x4124);
	CAM_write_reg(0xe014);
	CAM_write_reg(0x76ff);
	CAM_write_reg(0x33a0);
	CAM_write_reg(0x4220);
	CAM_write_reg(0x4318);
	CAM_write_reg(0x4c00);
	CAM_write_reg(0x87d0);
	CAM_write_reg(0x883f);
	CAM_write_reg(0xd703);
	CAM_write_reg(0xd910);
	CAM_write_reg(0xd382);
	CAM_write_reg(0xc808);
	CAM_write_reg(0xc980);
	CAM_write_reg(0x7c00);
	CAM_write_reg(0x7d02);
	CAM_write_reg(0x7c03);
	CAM_write_reg(0x7d48);
	CAM_write_reg(0x7d48);
	CAM_write_reg(0x7c08);
	CAM_write_reg(0x7d20);
	CAM_write_reg(0x7d10);
	CAM_write_reg(0x7d0e);
	CAM_write_reg(0x9000);
	CAM_write_reg(0x910e);
	CAM_write_reg(0x911a);
	CAM_write_reg(0x9131);
	CAM_write_reg(0x915a);
	CAM_write_reg(0x9169);
	CAM_write_reg(0x9175);
	CAM_write_reg(0x917e);
	CAM_write_reg(0x9188);
	CAM_write_reg(0x918f);
	CAM_write_reg(0x9196);
	CAM_write_reg(0x91a3);
	CAM_write_reg(0x91af);
	CAM_write_reg(0x91c4);
	CAM_write_reg(0x91d7);
	CAM_write_reg(0x91e8);
	CAM_write_reg(0x9120);
	CAM_write_reg(0x9200);
	CAM_write_reg(0x9306);
	CAM_write_reg(0x93e3);
	CAM_write_reg(0x9305);
	CAM_write_reg(0x9305);
	CAM_write_reg(0x9300);
	CAM_write_reg(0x9302);
	CAM_write_reg(0x9300);
	CAM_write_reg(0x9300);
	CAM_write_reg(0x9300);
	CAM_write_reg(0x9300);
	CAM_write_reg(0x9300);
	CAM_write_reg(0x9300);
	CAM_write_reg(0x9300);
	CAM_write_reg(0x9600);
	CAM_write_reg(0x9708);
	CAM_write_reg(0x9719);
	CAM_write_reg(0x9702);
	CAM_write_reg(0x970c);
	CAM_write_reg(0x9724);
	CAM_write_reg(0x9730);
	CAM_write_reg(0x9728);
	CAM_write_reg(0x9726);
	CAM_write_reg(0x9702);
	CAM_write_reg(0x9798);
	CAM_write_reg(0x9780);
	CAM_write_reg(0x9700);
	CAM_write_reg(0x9700);
	CAM_write_reg(0xc3ed);
	CAM_write_reg(0xa400);
	CAM_write_reg(0xa800);
	CAM_write_reg(0xc511);
	CAM_write_reg(0xc651);
	CAM_write_reg(0xbf80);
	CAM_write_reg(0xc710);
	CAM_write_reg(0xb666);
	CAM_write_reg(0xb8a5);
	CAM_write_reg(0xb764);
	CAM_write_reg(0xb97c);
	CAM_write_reg(0xb3af);
	CAM_write_reg(0xb497);
	CAM_write_reg(0xb5ff);
	CAM_write_reg(0xb0c5);
	CAM_write_reg(0xb194);
	CAM_write_reg(0xb20f);
	CAM_write_reg(0xc45c);
	CAM_write_reg(0xc0c8);
	CAM_write_reg(0xc196);
	CAM_write_reg(0x861d);
	CAM_write_reg(0x5000);
	CAM_write_reg(0x5190);
	CAM_write_reg(0x5218);
	CAM_write_reg(0x5300);
	CAM_write_reg(0x5400);
	CAM_write_reg(0x5588);
	CAM_write_reg(0x5700);
	CAM_write_reg(0x5a90);
	CAM_write_reg(0x5b18);
	CAM_write_reg(0x5c05);
	CAM_write_reg(0xc3ed);
	CAM_write_reg(0x7f00);
	CAM_write_reg(0xda04);
	CAM_write_reg(0xe51f);
	CAM_write_reg(0xe167);
	CAM_write_reg(0xe000);
	CAM_write_reg(0xdd7f);
	CAM_write_reg(0x0500);
	CAM_write_reg(0xff01);
	CAM_write_reg(0x0900);		//increase fan out of output driver
}

void CAM_init_YUV(void) {
	CAM_write_reg(0xFF00);
	CAM_write_reg(0xE004);
	CAM_write_reg(0xE167);
	CAM_write_reg(0xD701);	//Add 10/31/05
	CAM_write_reg(0xDA01);
	CAM_write_reg(0xD382);
	CAM_write_reg(0xE000);
	CAM_write_reg(0xFF01);
	CAM_write_reg(0x0C39);		// Single frame only
}

void CAM_init_RGB565(void) {
	CAM_write_reg(0xFF00);
	CAM_write_reg(0xE004);		// RESET: DVP on
	CAM_write_reg(0xE167);// Reserved
	CAM_write_reg(0xD701);// Reserved
	CAM_write_reg(0xDA08);		// RGB565; Byte swap enable for DVP: Low byte first UY or VY instead of YU or YV
	CAM_write_reg(0xC202);		// RGB_EN
	CAM_write_reg(0x9800);		// Reserved
	CAM_write_reg(0x9900);		// Reserved
	CAM_write_reg(0xD382);		// DVP auto mode;  DVP output speed control
	CAM_write_reg(0xE000);		// RESET: DVP off
//	CAM_write_reg(0xFF01);
//	CAM_write_reg(0x0C39);		// Single frame only
}

void CAM_init_RAW10(void) {
	CAM_write_reg(0xFF00);
	CAM_write_reg(0xE004);
	//CAM_write_reg(0xC202);
	CAM_write_reg(0xE167);
	CAM_write_reg(0xD701);	//Add 10/31/05
	CAM_write_reg(0xDA04);
	CAM_write_reg(0xD382);
	CAM_write_reg(0xE000);
//	CAM_write_reg(0xFF01);
//	CAM_write_reg(0x0C39);		// Single frame only
}

void CAM_UXGA_resolution(void) {
	CAM_write_reg(0xff01);	// Config sensor
	CAM_write_reg(0x3992);	// reserved
	CAM_write_reg(0x35da);	// reserved
	CAM_write_reg(0x221a);	// reserved
	CAM_write_reg(0x37c3);	// reserved
	CAM_write_reg(0x34c0);	// reserved; default is 0x20
	CAM_write_reg(0x0688);	// reserved
	CAM_write_reg(0x0d87);	// reserved
	CAM_write_reg(0x0e41);	// reserved
	CAM_write_reg(0x4622);	// Frame length adjustment LSB
	CAM_write_reg(0x1240);	// SVGA mode choose
	CAM_write_reg(0x1711);	// HREFST: set to default
	CAM_write_reg(0x1843);	// HREFEND: set to SVGA/CIF
	CAM_write_reg(0x1900);	// VSTRT: set to SVGA/CIF
	CAM_write_reg(0x1a4b);	// VEND: Vertical window line end MSB
	CAM_write_reg(0x3209);	// HREFST, HREFEND: set to SVGA/CIF
	CAM_write_reg(0x37c0);	// reserved (duplicate)
	CAM_write_reg(0x4fca);	// BD50: set to default
	CAM_write_reg(0x50a8);	// BD60: set to default
	CAM_write_reg(0x6d00);	// reserved
	CAM_write_reg(0x3d38);	// reserved

	CAM_write_reg(0xff00);	// Config DSP
	CAM_write_reg(0x883f);	// reserved
	CAM_write_reg(0xc064);	// HSIZE[10:3]
	CAM_write_reg(0xc14b);	// VSIZE[10:3]
	CAM_write_reg(0x861d);	// switch SDE on (bit 4)
	CAM_write_reg(0x51c8);	// H_SIZE[7:0] (real/4)
	CAM_write_reg(0x5296);	// V_SIZE[7:0] (real/4)
	CAM_write_reg(0x5500);	// V_SIZE[8] (bit 7); H_SIZE[8] (bit 3)
	CAM_write_reg(0x5ac8);	// OUTW[7:0] (real/4)
	CAM_write_reg(0x5b96);	// OUTH[7:0] (real/4)
	CAM_write_reg(0x5c00);	// OUTW[9:8] (bit 1:0); OUTH[8] (bit 2)
}

void CAM_SVGA_resolution(void) {
	CAM_write_reg(0xff01);	// Config sensor
	CAM_write_reg(0x3992);	// reserved
	CAM_write_reg(0x35da);	// reserved
	CAM_write_reg(0x221a);	// reserved
	CAM_write_reg(0x37c3);	// reserved
	CAM_write_reg(0x34c0);	// reserved; default is 0x20
	CAM_write_reg(0x0688);	// reserved
	CAM_write_reg(0x0d87);	// reserved
	CAM_write_reg(0x0e41);	// reserved
	CAM_write_reg(0x4622);	// Frame length adjustment LSB
	CAM_write_reg(0x1240);	// SVGA mode choose
	CAM_write_reg(0x030a);	// VEND, VSTRT 2LSBs
	CAM_write_reg(0x1711);	// HREFST: set to default
	CAM_write_reg(0x1843);	// HREFEND: set to SVGA/CIF
	CAM_write_reg(0x1900);	// VSTRT: set to SVGA/CIF
	CAM_write_reg(0x1a4b);	// VEND: Vertical window line end MSB (set to SVGA/CIF)
	CAM_write_reg(0x3209);	// HREFST, HREFEND: set to SVGA/CIF
	CAM_write_reg(0x37c0);	// reserved (duplicate)
	CAM_write_reg(0x4fca);	// BD50: set to default
	CAM_write_reg(0x50a8);	// BD60: set to default
	CAM_write_reg(0x6d00);	// reserved
	CAM_write_reg(0x3d38);	// reserved

	CAM_write_reg(0xff00);	// Config DSP
	CAM_write_reg(0x883f);	// reserved
	CAM_write_reg(0xc064);	// HSIZE[10:3]
	CAM_write_reg(0xc14b);	// VSIZE[10:3]
	CAM_write_reg(0x861d);	// switch SDE on (bit 4)
	CAM_write_reg(0x51c8);	// H_SIZE[7:0] (real/4)
	CAM_write_reg(0x5296);	// V_SIZE[7:0] (real/4)
	CAM_write_reg(0x5500);	// V_SIZE[8] (bit 7); H_SIZE[8] (bit 3)
	CAM_write_reg(0x5ac8);	// OUTW[7:0] (real/4)
	CAM_write_reg(0x5b96);	// OUTH[7:0] (real/4)
	CAM_write_reg(0x5c00);	// OUTW[9:8] (bit 1:0); OUTH[8] (bit 2)
}

void CAM_CIF_resolution(void) {
	CAM_write_reg(0xff01);	// Config sensor
	CAM_write_reg(0x3992);	// reserved
	CAM_write_reg(0x35da);	// reserved
	CAM_write_reg(0x221a);	// reserved
	CAM_write_reg(0x37c3);	// reserved
	CAM_write_reg(0x34c0);	// reserved; default is 0x20
	CAM_write_reg(0x0688);	// reserved
	CAM_write_reg(0x0d87);	// reserved
	CAM_write_reg(0x0e41);	// reserved
	CAM_write_reg(0x4622);	// Frame length adjustment LSB
	CAM_write_reg(0x1220);	// SVGA mode choose
	CAM_write_reg(0x0306);	// VEND, VSTRT 2LSBs
	CAM_write_reg(0x1711);	// HREFST: set to default
	CAM_write_reg(0x1843);	// HREFEND: set to SVGA/CIF
	CAM_write_reg(0x1900);	// VSTRT: set to SVGA/CIF
	CAM_write_reg(0x1a25);	// VEND: Vertical window line end MSB (set to SVGA/CIF)
	CAM_write_reg(0x3209);	// HREFST, HREFEND: set to SVGA/CIF
	CAM_write_reg(0x37c0);	// reserved (duplicate)
	CAM_write_reg(0x4fca);	// BD50: set to default
	CAM_write_reg(0x50a8);	// BD60: set to default
	CAM_write_reg(0x6d00);	// reserved
	CAM_write_reg(0x3d38);	// reserved

	CAM_write_reg(0xff00);	// Config DSP
	CAM_write_reg(0x883f);	// reserved
	CAM_write_reg(0x8c04);	// HSIZE[10:3]
	CAM_write_reg(0xc032);	// HSIZE[10:3]
	CAM_write_reg(0xc124);	// VSIZE[10:3]
	CAM_write_reg(0x861d);	// switch SDE on (bit 4)
	CAM_write_reg(0x5164);	// H_SIZE[7:0] (real/4)
	CAM_write_reg(0x5249);	// V_SIZE[7:0] (real/4)
	CAM_write_reg(0x5500);	// V_SIZE[8] (bit 7); H_SIZE[8] (bit 3)
	CAM_write_reg(0x5a64);	// OUTW[7:0] (real/4)
	CAM_write_reg(0x5b49);	// OUTH[7:0] (real/4)
	CAM_write_reg(0x5c00);	// OUTW[9:8] (bit 1:0); OUTH[8] (bit 2)
}

/*
 *  Return the difference between two struct timevals in microseconds
 */
long tvdelta(struct timeval *t1, struct timeval *t2)
{
	long delta, usec;

	delta = 1000000 * (t1->tv_sec - t2->tv_sec);
	usec = t1->tv_usec;
	if (t1->tv_usec < t2->tv_usec) {
		usec += 1000000;
		delta -= 1000000;
	}
	delta += (usec - t2->tv_usec);

	return delta;
}

long getoffset(void)
{
	int i;
	struct timeval t, o;
	long delta = 0;

	for (i = 0; i < AVERAGE; i++) {
		gettimeofday(&o, NULL);
		gettimeofday(&t, NULL);
		delta += tvdelta(&t, &o);
	}

	return (delta / AVERAGE);
}

void mydelay(unsigned int delay)
{
	clock_t goal = delay * CLOCKS_PER_SEC / 1000 + clock();
	while (goal > clock()) ;
}