cam2tft.c

This is the source code of Camera driver for OV2640 camera from OmniVision using in Blackfin platfor

	fd = open("/dev/fb0", O_RDWR);
	if(fd < 0)
		{
			printf("cannot open /dev/fb0\n");
			exit(0);
		}

	ioctl(fd, FBIOGET_VSCREENINFO, &initial_vi);
	initial_vi.xoffset = initial_vi.yoffset = 0;
	ioctl(fd, FBIOGET_VSCREENINFO, &vi);
	framebase = mmap(0, vi.xres * vi.yres*2, PROT_READ|PROT_WRITE, MAP_PRIVATE, fd, 0);
	tft_width = vi.xres;
	tft_height = vi.yres;
}

void TFT_Display (unsigned char *RGBbuffer, int row_size, int col_size, int tft_width, int tft_height) {
	unsigned short *pDraw = framebase;
	int x;
	int y;
	int mod_x = row_size/tft_width;
	int mod_y = col_size/tft_height - 1;
	int res_x = row_size - mod_x*tft_width;
	int res_y = col_size - (mod_y+1)*tft_height;
	RGBbuffer += (row_size*(res_y/2)*3 + res_x/2*3);
	for (y = 0;y<tft_height;y++){
		for (x=0;x<tft_width;x++){
			*(pDraw++) = (((*(RGBbuffer  ) & 0x00F8) << 8) |		// 5 bits Blue
						  ((*(RGBbuffer+1) & 0x00FC) << 3) |		// 6 bits Green
						  ((*(RGBbuffer+2) & 0x00F8) >> 3));		// 5 bits Red
			
			RGBbuffer += mod_x*3;		// 3 bytes for each pixel, bypass 5 pixel to scale down
		}
		RGBbuffer += (mod_y*row_size*3 + res_x*3);
	}
}

void TFT565_DirectDisplay (unsigned char *RAW8buffer, int row_size, int col_size, int tft_width, int tft_height) {
	unsigned short *pDraw = framebase;
	int x, y;
	int mod_x = row_size/tft_width/2;
	mod_x *= 2;
	int mod_y = col_size/tft_height/2;
	mod_y = mod_y*2 - 1;
	int res_x = row_size - mod_x*tft_width;
	int res_y = col_size - (mod_y+1)*tft_height;
	RAW8buffer += (row_size*(res_y/2) + res_x/2);
	for (y = 0;y<tft_height;y++){
		for (x=0;x<tft_width;x++){
			*(pDraw++) = (((*(RAW8buffer) & 0x00F8) << 8) |		// 5 bits Blue
						  ((((*(RAW8buffer+1) + *(RAW8buffer+row_size))/2) & 0x00FC) << 3) |		// 6 bits Green
						  ((*(RAW8buffer+row_size+1) & 0x00F8) >> 3));		// 5 bits Red
			
			RAW8buffer += mod_x;		// Bypass some pixels for scale down
		}
		RAW8buffer += (mod_y*row_size + res_x);
	}
}
/*
void TFT565_DirectDisplay (unsigned char *RAW8buffer, int row_size, int col_size, int tft_width, int tft_height) {
	// This function is specific for using with input 800x600 and output 320x240
	unsigned short *pDraw = framebase;
	int x, y;
	//RAW8buffer += (row_size*(res_y/2) + res_x/2);
	for (y = 0;y<240;y++){
		for (x=0;x<320;x++){
			*(pDraw++) = (((*(RAW8buffer) & 0x00F8) << 8) |		// 5 bits Blue
						  ((((*(RAW8buffer+1) + *(RAW8buffer+800))/2) & 0x00FC) << 3) |		// 6 bits Green
						  ((*(RAW8buffer+801) & 0x00F8) >> 3));		// 5 bits Red
			
			RAW8buffer += 2;		// Bypass some pixels for scale down
		}
		RAW8buffer += 960;
	}
}
*/
void TFT565_Display (unsigned char *RGB565buffer, int row_size, int tft_width, int tft_height) {
	unsigned short *pDraw = framebase;
	int x;
	int y;
	for (y = 0;y<tft_height;y++){
		for (x=0;x<tft_width;x++){
			*(pDraw++) = (((*(RGB565buffer+1) << 8) & 0xFF00) | (*(RGB565buffer) & 0x00FF));
			RGB565buffer += (row_size/tft_width)*2;	// 2 bytes for each pixel, bypass 5 pixel to scale down
		}
		//RGB565buffer += (row_size-tft_width)*2;
		RGB565buffer += 4*row_size*2;
		//RGB565buffer += 19200;
	}
}

void CAM_raw_init(void){
	CAM_write_reg(0xFF01); 
	CAM_write_reg(0x1280); 
	CAM_write_reg(0xFF00); 
	CAM_write_reg(0x2CFF); 
	CAM_write_reg(0x2EDF); 
	CAM_write_reg(0xFF01); 
	CAM_write_reg(0x3C32); 
	CAM_write_reg(0x1100); // clk divider 
	CAM_write_reg(0x0902); 
	CAM_write_reg(0x0428); 
	CAM_write_reg(0x13E0); // AEC/AGC off 
	CAM_write_reg(0x1448); 
	CAM_write_reg(0x2C0C); // reserved 
	CAM_write_reg(0x3378); // reserved 
	CAM_write_reg(0x3A33); // reserved 
	CAM_write_reg(0x3BFB); // reserved 
	CAM_write_reg(0x3E00); // reserved 
	CAM_write_reg(0x4311); // reserved 
	CAM_write_reg(0x1610); // reserved 
	CAM_write_reg(0x3902); // reserved 
	CAM_write_reg(0x35DA); // reserved 
	CAM_write_reg(0x221A); // reserved 
	CAM_write_reg(0x37C3); // reserved 
	CAM_write_reg(0x2300); // reserved 
	CAM_write_reg(0x34C0); // reserved 
	CAM_write_reg(0x361A); // reserved 
	CAM_write_reg(0x0688); // reserved 
	CAM_write_reg(0x07C0); // reserved 
	CAM_write_reg(0x0D87); 
	CAM_write_reg(0x0E41); // reserved 
	CAM_write_reg(0x4C00); // reserved 
	CAM_write_reg(0x4A81); // reserved 
	CAM_write_reg(0x2199); // reserved 
	CAM_write_reg(0x2440); 
	CAM_write_reg(0x2538); 
	CAM_write_reg(0x2682); 
	CAM_write_reg(0x5C00); 
	CAM_write_reg(0x6300); 
	CAM_write_reg(0x6170); 
	CAM_write_reg(0x6280); 
	CAM_write_reg(0x7C05); // reserved 
	CAM_write_reg(0x2080); // reserved 
	CAM_write_reg(0x2830); // reserved 
	CAM_write_reg(0x6C00); // reserved 
	CAM_write_reg(0x6E00); // reserved 
	CAM_write_reg(0x7002); // reserved 
	CAM_write_reg(0x7194); // reserved 
	CAM_write_reg(0x73c1); // reserved 
//	CAM_write_reg(0x3D34); 
	CAM_write_reg(0x5A57); 
	CAM_write_reg(0x4FBB); 
	CAM_write_reg(0x509C); 
	CAM_write_reg(0xFF00); 
	CAM_write_reg(0xE57F); // Bypass DSP 
	CAM_write_reg(0xF9C0); // Bypass DSP 
	CAM_write_reg(0x4124); 
	CAM_write_reg(0xE014); 
	CAM_write_reg(0x76FF); // Bypass DSP 
	CAM_write_reg(0x33A0); 
	CAM_write_reg(0x4220); 
	CAM_write_reg(0x4318); 
	CAM_write_reg(0x4C00); 
//	CAM_write_reg(0x87D0); 
	CAM_write_reg(0x883F); 
	CAM_write_reg(0xD703); 
	CAM_write_reg(0xD910); 
	CAM_write_reg(0xD382); 
	CAM_write_reg(0xC808); 
	CAM_write_reg(0xC980); 
	CAM_write_reg(0x7C00);// SDE command 
	CAM_write_reg(0x7D00); 
	CAM_write_reg(0x7C03); 
	CAM_write_reg(0x7D48); 
	CAM_write_reg(0x7D48); 
	CAM_write_reg(0x7C08); 
	CAM_write_reg(0x7D20); 
	CAM_write_reg(0x7D10); 
	CAM_write_reg(0x7D0E); 
	CAM_write_reg(0x9200); 
	CAM_write_reg(0x9306); 
	CAM_write_reg(0x93E4); 
	CAM_write_reg(0x9305); 
	CAM_write_reg(0x9305); 
	CAM_write_reg(0x9300); 
	CAM_write_reg(0x9304); 
	CAM_write_reg(0x9300); 
	CAM_write_reg(0x9300); 
	CAM_write_reg(0x9300); 
	CAM_write_reg(0x9300); 
	CAM_write_reg(0x9300); 
	CAM_write_reg(0x9300); 
	CAM_write_reg(0x9300); 
	CAM_write_reg(0xC3ED); 
	CAM_write_reg(0xA400); 
	CAM_write_reg(0xA800); 
	CAM_write_reg(0xC511); 
	CAM_write_reg(0xC651); 
	CAM_write_reg(0xBF80); 
	CAM_write_reg(0xC710); 
	CAM_write_reg(0xB666); 
	CAM_write_reg(0xB8A5); 
	CAM_write_reg(0xB764); 
	CAM_write_reg(0xB97C); 
	CAM_write_reg(0xB3AF); 
	CAM_write_reg(0xB497); 
	CAM_write_reg(0xB5FF); 
	CAM_write_reg(0xB0C5); 
	CAM_write_reg(0xB194); 
	CAM_write_reg(0xB20F); 
	CAM_write_reg(0xB45C); 
	CAM_write_reg(0xC0C8); 
	CAM_write_reg(0xC196); 
	CAM_write_reg(0x861D); 
	CAM_write_reg(0x5000); 
	CAM_write_reg(0x5190); 
	CAM_write_reg(0x5218); 
	CAM_write_reg(0x5300); 
	CAM_write_reg(0x5400); 
	CAM_write_reg(0x5588); 
	CAM_write_reg(0x5700); 
	CAM_write_reg(0x5A90); 
	CAM_write_reg(0x5B18); 
	CAM_write_reg(0x5C05); 
	CAM_write_reg(0xC3ED); 
	CAM_write_reg(0x7F00); 
	CAM_write_reg(0xDA04); 
	CAM_write_reg(0xE51F); 
	CAM_write_reg(0xE167); 
	CAM_write_reg(0xE000); 
	CAM_write_reg(0xDD7F); 
	CAM_write_reg(0x0500); 
	CAM_write_reg(0xFF01); 
	CAM_write_reg(0x2A30); 
	CAM_write_reg(0x2B00); 
	CAM_write_reg(0x1100); 
	CAM_write_reg(0x1240); // SVGA mode 
	CAM_write_reg(0x1711); 
	CAM_write_reg(0x1843); 
	CAM_write_reg(0x1900); 
	CAM_write_reg(0x1A4B); 
	CAM_write_reg(0x3209); 
	CAM_write_reg(0x0304); 
	CAM_write_reg(0x3D38); 
	CAM_write_reg(0x3912); 
	CAM_write_reg(0x35DA); 
	CAM_write_reg(0x221A); 
	CAM_write_reg(0x37C3); 
	CAM_write_reg(0x2300); 
	CAM_write_reg(0x34A0); 
	CAM_write_reg(0x361A); 
	CAM_write_reg(0x0688); 
	CAM_write_reg(0x07C0); 
	CAM_write_reg(0x0D87); 
	CAM_write_reg(0x0E41); 
	CAM_write_reg(0x4C00); 
	CAM_write_reg(0x6320);// CIP RAW 
	CAM_write_reg(0xFF00); 
	CAM_write_reg(0xC066); 
	CAM_write_reg(0xC14C); 
	CAM_write_reg(0x8C06); 
	CAM_write_reg(0x8635); 
	CAM_write_reg(0x5000); 
	CAM_write_reg(0x51CC); 
	CAM_write_reg(0x5299); 
	CAM_write_reg(0x5300); 
	CAM_write_reg(0x5400); 
	CAM_write_reg(0x5500); 
	CAM_write_reg(0x5ACC); 
	CAM_write_reg(0x5B99); 
	CAM_write_reg(0x5C00); 
	CAM_write_reg(0xD382); 
	CAM_write_reg(0xDA04); 
	CAM_write_reg(0xE51F); 
	CAM_write_reg(0xE167); 
	CAM_write_reg(0xE000); 
	CAM_write_reg(0xDD7F); 
	CAM_write_reg(0x0500); 
	CAM_write_reg(0x8750);// Pixel correction on 
	CAM_write_reg(0xC381); 
	CAM_write_reg(0xC201);// raw 
	CAM_write_reg(0x9271); 
	CAM_write_reg(0x9300); 
	CAM_write_reg(0x9200); 
	CAM_write_reg(0x9300); 
	CAM_write_reg(0x4FCA); // 50Hz banding 
	CAM_write_reg(0x50A8); // 60Hz banding 
	CAM_write_reg(0xFF00); 
	CAM_write_reg(0xFF01); 
	CAM_write_reg(0x0F43); // reserved 
	CAM_write_reg(0x2D00); // VSYNC pulse width 
	CAM_write_reg(0x2E00); // VSYNC pulse width 
	CAM_write_reg(0x1101); // clock divider 
	CAM_write_reg(0x1240); // SVGA mode 
	CAM_write_reg(0x1710); 
	CAM_write_reg(0x1843); 
	CAM_write_reg(0x1900); 
	CAM_write_reg(0x1A4d); 
	CAM_write_reg(0xFF01); 
	CAM_write_reg(0x1101); // clock divider 
	CAM_write_reg(0x3D38); // reserved 
	CAM_write_reg(0x13C0); // turn off AGC/AEC 
	CAM_write_reg(0x0000); // global gain 
	CAM_write_reg(0x0428); 
	CAM_write_reg(0x1033); // exposure line 
	CAM_write_reg(0x4500); // AGC/AEC
}

void CAM_raw_preview(void){
	CAM_write_reg(0xFF01); 
	CAM_write_reg(0x1240);  // change to SVGA(800x600) mode 
	
	// setup sensor output ROI 
	CAM_write_reg(0x1711);  // HREFST 8MSBs
	CAM_write_reg(0x1843);  // HREFEND 8MSBs
	CAM_write_reg(0x3209);  // HREFST, HREFEND 3 LSBs
	CAM_write_reg(0x1900);  // VSTRT 8MSBs
	CAM_write_reg(0x1A4B);  // VEND 8MSBs
	CAM_write_reg(0x030A);  // VEND, VSTRT 2LSBs

	CAM_write_reg(0x4FCA);  // 50Hz banding AEC 8 LSBs 
	CAM_write_reg(0x50A8);  // 60Hz banding AEC 8 LSBs 

	CAM_write_reg(0x6D00);  // reserved //???? 
	CAM_write_reg(0x3D38);  // PLL/divider setting 
	CAM_write_reg(0x3912);  // PWCOM1, reserved 
	CAM_write_reg(0x35DA);  // reserved 
	
	CAM_write_reg(((0x22<<8)&0xFF00) | ((CAM_read_reg(0x22) | 0x10)&0xFF));  // ANCOM3 
	
	CAM_write_reg(0x37C3);  // reserved 
	CAM_write_reg(0x2300);  // reserved 
	CAM_write_reg(0x34A0);  // ARCOM2, reserved 
	CAM_write_reg(0x361A);  // reserved 
	CAM_write_reg(0x0688);  // reserved 
	CAM_write_reg(0x07C0);  // reserved 
	CAM_write_reg(0x0D87);  // reserved 
	CAM_write_reg(0x0E41);  // reserved 
	CAM_write_reg(0x4C00);  // reserved 

	CAM_write_reg(0xFF00); 
	CAM_write_reg(0xC064);  // HSIZE
	CAM_write_reg(0xC14B);  // VSIZE
	CAM_write_reg(0x8C00);  // HSIZE, VSIZE
//	CAM_write_reg(0x8C06);  // HSIZE, VSIZE
	CAM_write_reg(0x8635);  // CTRL2
	CAM_write_reg(0x5000);  // CTRL1

	CAM_write_reg(0x51C8);  // H_SIZE
	CAM_write_reg(0x5296);  // V_SIZE

	CAM_write_reg(0x5300);  // OFFSET_X
	CAM_write_reg(0x5400);  // OFFSET_Y
	CAM_write_reg(0x5500);  // H_SIZE, V_SIZE, OFFSET_X, OFFSET_Y

	CAM_write_reg(0x5AC8);  // OUTW
	CAM_write_reg(0x5B96);  // OUTH
	CAM_write_reg(0x5C00);  // OUTH, OUTW
	CAM_write_reg(0xD382);  // DVP speed control

	CAM_write_reg(0xE51F);  // reserved
	CAM_write_reg(0xE167);  // reserved
	CAM_write_reg(0xE000);  // RESET
	CAM_write_reg(0xDD7F);  // reserved
	CAM_write_reg(0x0500);  // use DSP

//	CAM_write_reg(0x87D0);  // Black & White Pixel Canceling
	CAM_write_reg(0xC381);  // CTRL1: CIP, PRE
	CAM_write_reg(0xC201);  // CTRL0: RAW_EN
	CAM_write_reg(0x9201);  // reserved
	CAM_write_reg(0x9300);  // reserved
	CAM_write_reg(0x9200);  // reserved
	CAM_write_reg(0x9300);  // reserved
}

void CAM_raw_capture(void){
	/*Switch mode to 1600x1200*/ 
	CAM_write_reg(0xFF01); 
	CAM_write_reg(0x1200);  // switch to UXGA(1600x1200) mode 
	 
	// setup sensor output ROI 
	CAM_write_reg(0x1711);  // HREFST 8MSBs
	CAM_write_reg(0x1875);  // HREFEND 8MSBs
	CAM_write_reg(0x3236);  // HREFST, HREFEND 3 LSBs
	CAM_write_reg(0x1901);  // VSTRT 8MSBs
	CAM_write_reg(0x1A97);  // VEND 8MSBs
	CAM_write_reg(0x030F);  // VEND, VSTRT 2LSBs

	CAM_write_reg(0x4FBB);  // 50Hz banding AEC 8 LSBs 
	CAM_write_reg(0x509C);  // 60Hz banding AEC 8 LSBs 
	CAM_write_reg(0x5A57);  // 50/60Hz banding AEC maximum steps 
	CAM_write_reg(0x6D80);  // reserved 
//	CAM_write_reg(0x3D34);  // PLL/divider setting 
	CAM_write_reg(0x3D38);  // PLL/divider setting 

	CAM_write_reg(0x3902);  // PWCOM1, reserved 
	CAM_write_reg(0x3588);  // reserved 
//iTemp = read_cmos_sensor(0x22); // ANCOM3 
//write_cmos_sensor(0x22, iTemp & 0xEF); 
	 
	CAM_write_reg(0x3740);  // reserved 
	CAM_write_reg(0x2300);  // reserved 
	CAM_write_reg(0x34A0);  // ARCOM2, reserved 
	CAM_write_reg(0x361A);  // reserved 
	CAM_write_reg(0x0602);  // reserved 
	CAM_write_reg(0x07C0);  // reserved 
	CAM_write_reg(0x0DB7);  // reserved 
	CAM_write_reg(0x0E01);  // reserved 
	CAM_write_reg(0x4C00);  // reserved 

	CAM_write_reg(0xFF00); 
	CAM_write_reg(0xC0C8);  // HSIZE
	CAM_write_reg(0xC196);  // VSIZE
	CAM_write_reg(0x8C00);  // HSIZE, VSIZE