bfin_ppifcd.h

This is the source code of Camera driver for OV2640 camera from OmniVision using in Blackfin platfor

/*
 * File:         drivers/char/bfin_ppifcd.h
 * Based on:
 * Author:       Michael Hennerich
 *
 * Created:      12.07.2005 17:09
 * Description:  Simple PPI Frame Capture driver for ADSP-BF5xx
 *
 * Rev:          $Id: bfin_ppifcd.h 4054 2007-12-18 07:39:37Z hennerich $
 *
 * Modified:
 *               Copyright 2005-2006 Analog Devices Inc.
 *
 * Bugs:         Enter bugs at http://blackfin.uclinux.org/
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, see the file COPYING, or write
 * to the Free Software Foundation, Inc.,
 * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 */

#ifndef _ADSP_PPIADC_H_
#define _ADSP_PPIADC_H_

#define PPI_READ              0
#define PPI_WRITE             1

#define CMD_PPI_SET_PIXELS_PER_LINE   0
#define CMD_PPI_SET_LINES_PER_FRAME   1
#define CMD_PPI_SET_PPICONTROL_REG    2
#define CMD_PPI_SET_PPIDELAY_REG      3
#define CMD_PPI_SET_PPICOUNT_REG      4
#define CMD_SET_TRIGGER_GPIO          5
#define CMD_PPI_GET_SYSTEMCLOCK       6
#define CMD_PPI_GET_ALLCONFIG 		  7 /* For debug */

#define TRIGGER_PF0 0
#define TRIGGER_PF1 1
#define TRIGGER_PF2 2
#define TRIGGER_PF3 3
#define TRIGGER_PF4 4
#define TRIGGER_PF5 5
#define TRIGGER_PF6 6
#define TRIGGER_PF7 7
#define TRIGGER_PF8 8
#define TRIGGER_PF9 9
#define TRIGGER_PF10 10
#define TRIGGER_PF11 11
#define TRIGGER_PF12 12
#define TRIGGER_PF13 13
#define TRIGGER_PF14 14
#define TRIGGER_PF15 15

#define NO_TRIGGER  (-1)


/* Some Sensor Sepcific Defaults */

#define OV2640FSL
#undef MT9M001
#undef  MT9V022

#ifdef OV2640FSL
//refer to include/asm/mach-bf561/defBF561.h
#define POL_C 			0x0000				//Data valid at posedge clk (to revert polarity, use 0x4000)
#define POL_S 			0x0000				//HSYNC, VSYNC is active high (to active low, use 0x8000)
#define PIXEL_PER_LINE	1600
#define LINES_PER_FRAME	1200
#define CFG_GP_Input_3Syncs 	0x0020		//Use 2 Sync (mask is 0x0030)
#define GP_Input_Mode			0x000C		//Global Purpose mode; other mode is ITU-656... ITU-656 doesn't use CLK or SYNC, it detects embeded frame preamble
#define PPI_DATA_LEN				DLEN_8		//Use DLEN_8 or DLEN(x) for 10 <= x <= 16
//#define PPI_DATA_LEN				DLEN(10)
#define PPI_PACKING					0x0000			// Don't use Packing
//#define PPI_PACKING					PACK_EN		//two 8-bits sample pack into one 16-bits for highest throughput
/* **********  PPI_CONTROL Masks  ************************ */
	//#define PORT_DIR             0x00000002	/* PPI Port Direction       */
	//#define FLD_SEL              0x00000040	/* PPI Active Field Select */
	//#define PACK_EN              0x00000080	/* PPI Packing Mode */
	//#define DMA32                0x00000100	/* PPI 32-bit DMA Enable */
	//#define SKIP_EN              0x00000200	/* PPI Skip Element Enable */
	//#define SKIP_EO              0x00000400	/* PPI Skip Even/Odd Elements */
	//#define DLENGTH              0x00003800	/* PPI Data Length  */
/***********************/
#define DMA_FLOW_MODE			0x0000 //STOPMODE
#define DMA_WDSIZE				WDSIZE_8
/* **********  DMA CONTROLLER MASKS  ********************* */
	//#define DMAEN	        0x00000001	/* Channel Enable */
	//#define WNR	   	0x00000002	/* Channel Direction (W/R*) */
	//#define WDSIZE_8	0x00000000	/* Word Size 8 bits */
	//#define WDSIZE_16	0x00000004	/* Word Size 16 bits */
	//#define WDSIZE_32	0x00000008	/* Word Size 32 bits */
	//#define DMA2D	        0x00000010	/* 2D/1D* Mode */
	//#define RESTART         0x00000020	/* Restart */
	//#define DI_SEL	        0x00000040	/* Data Interrupt Select */
	//#define DI_EN	        0x00000080	/* Data Interrupt Enable */
	//#define DMAFLOW	        0x00007000	/* Flow Control */
	//#define DMAFLOW_STOP		0x0000	/* Stop Mode */
	//#define DMAFLOW_AUTO		0x1000	/* Autobuffer Mode */
	//#define DMAFLOW_ARRAY		0x4000	/* Descriptor Array Mode */
	//#define DMAFLOW_SMALL		0x6000	/* Small Model Descriptor List Mode */
	//#define DMAFLOW_LARGE		0x7000	/* Large Model Descriptor List Mode */
/* Bit position for shift register mask */
	//#define DMAEN_P	            	0	/* Channel Enable */
	//#define WNR_P	            	1	/* Channel Direction (W/R*) */
	//#define DMA2D_P	        	4	/* 2D/1D* Mode */
	//#define RESTART_P	      	5	/* Restart */
	//#define DI_SEL_P	     	6	/* Data Interrupt Select */
	//#define DI_EN_P	            	7	/* Data Interrupt Enable */
#endif

#endif /* _ADSP_PPIADC_H_ */