cache.c

smdk40100 40mhz test code

#include <string.h>
#include "..\include\k401.h"
#include "..\include\k401lib.h"
#include "..\include\option.h"

void MarchCMinus32(int address,int unit,unsigned int pattern);
void _MarchSub1(unsigned int *pt,int unit,unsigned int pattern,int incdec);
int marchError;

int Test_Cache(void)
{
    int saveSyscfg;

    saveSyscfg=rSYSCFG;
    marchError=0;


    rSYSCFG=(MEMORY1_ROM|MEMORY0_SDRAM|ADDRESS_MUX_OFF|SYSCFG_4KB|SFR_STARTADDRESS|WRBUF_OFF|CACHE_OFF|STALL_OFF );
    // 
    // Set 0 : 0x10000000 ~ 0x100007fc
    // Set 1 : 0x10800000 ~ 0x108007fc
    // TagRAM : 0x11000000 ~ 0x110001fc

    Uart_Printf("March-10 Test : Cache Mode = 4KB, Internal SRAM = 0KB\n");
    MarchCMinus32(0x10000000,511,0x00000000);
    MarchCMinus32(0x10000000,511,0x0f0f0f0f);
    MarchCMinus32(0x10000000,511,0x33333333);
    MarchCMinus32(0x10000000,511,0x55555555);
    Uart_Printf("March-10 Test : Set 0 is tested!\n");

    MarchCMinus32(0x10800000,511,0x00000000);
    MarchCMinus32(0x10800000,511,0x0f0f0f0f);
    MarchCMinus32(0x10800000,511,0x33333333);
    MarchCMinus32(0x10800000,511,0x55555555);
    Uart_Printf("March-10 Test : Set 1 is tested!\n");

    MarchCMinus32(0x11000000,127,0x00000000);
    MarchCMinus32(0x11000000,127,0x0000ffff);
    MarchCMinus32(0x11000000,127,0x00ff00ff);
    MarchCMinus32(0x11000000,127,0x0f0f0f0f);
    MarchCMinus32(0x11000000,127,0x33333333);
    MarchCMinus32(0x11000000,127,0x55555555);
    Uart_Printf("March-10 Test : TagRAM is tested!\n");

    rSYSCFG=(MEMORY1_ROM|MEMORY0_SDRAM|ADDRESS_MUX_OFF|SYSCFG_2KB|SFR_STARTADDRESS|WRBUF_OFF|CACHE_OFF|STALL_OFF );
    // 
    // Set 0 : 0x10000000 ~ 0x100003fc
    // Set 1 : 0x10800000 ~ 0x108003fc
    // TagRAM : 0x11000000 ~ 0x110000fc
    // Internal SRAM : SFR_STARTADDRESS+0 ~ SFR_STARTADDRESS+0x7ff

    Uart_Printf("March-10 Test : Cache Mode = 2KB, Internal SRAM = 2KB\n");
    MarchCMinus32(0x10000000,255,0x00000000);
    MarchCMinus32(0x10000000,255,0x0f0f0f0f);
    MarchCMinus32(0x10000000,255,0x33333333);
    MarchCMinus32(0x10000000,255,0x55555555);
    Uart_Printf("March-10 Test : Set 0 is tested!\n");

    MarchCMinus32(0x10800000,255,0x00000000);
    MarchCMinus32(0x10800000,255,0x0f0f0f0f);
    MarchCMinus32(0x10800000,255,0x33333333);
    MarchCMinus32(0x10800000,255,0x55555555);
    Uart_Printf("March-10 Test : Set 1 is tested!\n");

    MarchCMinus32(0x11000000,63,0x00000000);
    MarchCMinus32(0x11000000,63,0x0000ffff);
    MarchCMinus32(0x11000000,63,0x00ff00ff);
    MarchCMinus32(0x11000000,63,0x0f0f0f0f);
    MarchCMinus32(0x11000000,63,0x33333333);
    MarchCMinus32(0x11000000,63,0x55555555);
    Uart_Printf("March-10 Test : TagRAM is tested!\n");

    MarchCMinus32(_CPU_ASICBASE,511,0x00000000);
    MarchCMinus32(_CPU_ASICBASE,511,0x0f0f0f0f);
    MarchCMinus32(_CPU_ASICBASE,511,0x33333333);
    MarchCMinus32(_CPU_ASICBASE,511,0x55555555);
    Uart_Printf("March-10 Test : Internal SRAM is tested!\n");

    rSYSCFG=(MEMORY1_ROM|MEMORY0_SDRAM|ADDRESS_MUX_OFF|SYSCFG_0KB|SFR_STARTADDRESS|WRBUF_OFF|CACHE_OFF|STALL_OFF );
    // 
    // Internal SRAM : SFR_STARTADDRESS+0 ~ SFR_STARTADDRESS+0xfff

    Uart_Printf("March-10 Test : Cache Mode = 0KB, Internal SRAM = 4KB\n");

    MarchCMinus32(_CPU_ASICBASE,1023,0x00000000);
    MarchCMinus32(_CPU_ASICBASE,1023,0x0f0f0f0f);
    MarchCMinus32(_CPU_ASICBASE,1023,0x33333333);
    MarchCMinus32(_CPU_ASICBASE,1023,0x55555555);
    Uart_Printf("March-10 Test : Internal SRAM is tested!\n");

    rSYSCFG=saveSyscfg;

    if(marchError==0)return 1; else return 0;
}

int Test_ISRAM(void)
{
    int i,k,Error,j;
    int saveSyscfg;

    saveSyscfg=rSYSCFG;
    rSYSCFG=(MEMORY1_ROM|MEMORY0_SDRAM|ADDRESS_MUX_OFF|SYSCFG_0KB|SFR_STARTADDRESS|WRBUF_OFF|CACHE_OFF|STALL_OFF);

    for(k=0;k<8;k++)
    {
	if(k==0)j=0x00;
	else if(k==1)j=0xff;
	else if(k==2)j=0x0f;
	else if(k==3)j=0xf0;
	else if(k==4)j=0x55;
	else if(k==5)j=0xaa;
	else if(k==6)j=0x33;
	else if(k==7)j=0xcc;

	for(i=0;i<0x1000;i++)
	    *((unsigned char *)(_CPU_ASICBASE+i))=j;

	Error=0;
	for(i=0;i<0x1000;i++)
	{
	    if(*((unsigned char *)(_CPU_ASICBASE+i))!=j)
	    {
		Uart_Printf("Address=0x%x, DaTa=0x%x Real Data=0x%x\n",(_CPU_ASICBASE+i),*((unsigned char *)(_CPU_ASICBASE+i)),j);
		Error++;
	    }
	}
    }

    Flush_Cache();
    rSYSCFG=saveSyscfg;

    if(Error==0){Uart_Printf("SRAM Read/Write Test OK!!!\n"); return 1;}
    else {Uart_Printf("SRAM Read/Write Test Fail!!!\n"); return 0;}

}

void MarchCMinus32(int address,int unit,unsigned int pattern)
{
    int i;
    unsigned int *tempPt;
    
    tempPt=(unsigned int *)address;
    
    for(i=0;i<=unit;i++)
    {
        *tempPt++=pattern;
    }
    
    _MarchSub1((unsigned int *)address,unit,~pattern,1);
    _MarchSub1((unsigned int *)address,unit,pattern,1);
    _MarchSub1((unsigned int *)address+unit,unit,~pattern,-1);
    _MarchSub1((unsigned int *)address+unit,unit,pattern,-1); 
    
    tempPt=(unsigned int *)address;
    for(i=0;i<=unit;i++)
    {	
        if(*tempPt!=pattern){marchError=1;Uart_Printf("ERROR0:%x\n",tempPt);}
        tempPt++;
    }
}


void _MarchSub1(unsigned int *pt,int unit,unsigned int pattern,int incdec)
{
    unsigned int i,rp;
    
    for(i=0;i<=unit;i++)
    {
        rp=*pt;
        *pt=pattern;
        
        if(rp!=(~pattern)){marchError=1;Uart_Printf("ERROR1:A=%x,RP=%x,WP=%x\n",pt,rp,(~pattern));}
        pt+=incdec;
    }
}