k401init.s

smdk40100 40mhz test code

;;	ldr	r0,	=0xff
;;	strb	r0,	[r1]

;;	Port 8 Configuration
;;	P8.7  P8.6  P8.5  P8.4  P8.3  P8.2  P8.1  P8.0
;;	IN    IN    IN    IN    IN    IN    IN    IN
;;      0     0     0     0     0     0     0     0	(0000 0000)
;;	UP    UP    UP	  UP    UP    UP    UP    UP	(1111 1111)

;;	ldr	r1,	=PCON8
;;	ldr	r0,	=0x0
;;	strb	r0,	[r1]

;;	ldr	r1,	=PUR8
;;	ldr	r0,	=0xff
;;	strb	r0,	[r1]

;; System Control configuration
;;    - Grobal interrupt mask, System Clock=MCLK, Normal operation


	ldr	r0,	=SYSCON
	mov	r1,	#0x18
	strb	r1,	[r0]

;; All Interrupt Disable

	ldr	r0,	=INTMOD
	mov	r1,	#0x0			; All IRQ
	str	r1,	[r0]

	ldr	r0,	=INTMSK
	mov	r1,	#0x0
	str	r1,	[r0]			; All disable

;; Configuration memory allocation
;; This operation must be performed immediately

	ldr	r0,	=SMRDATA		; Load address of area 'SMRDATA'
	ldmia	r0,	{r1-r9}			; Load each word value of 'SMRDATA'
	ldr	r0,	=MEMCON0		; MEMBANK0 offset : 0x2000
	stmia	r0,	{r1-r9}			; Store each 'SMRDATA' value to the system manager registers

	ldr	sp,	=SVCStack

	bl	InitStacks

;;
	ldr	r0,	=HandleIRQ
	ldr	r1,	=IsrIRQ
	str	r1,	[r0]

;; --------------------------------------------------------------------------------------------------
;; Initialization for C source program
;; --------------------------------------------------------------------------------------------------
;; Initialize memory required for C code
;;   - RAM initialization
;;   - Copy all read/write data from Assembler & C code to the read/write area
;;   - Copy Zero initialized data from C code to the read/write area(for example, global variable)
;; --------------------------------------------------------------------------------------------------

	LDR	r0,	=|Image$$RO$$Limit|	; Get pointer to ROM data
	LDR	r1,	=|Image$$RW$$Base|	; and RAM copy
	LDR	r3,	=|Image$$ZI$$Base|	; Zero init base => top of initialized data

	CMP	r0,	r1			; Check that they are different
	BEQ	%F1

0
	CMP	r1,	r3
	LDRCC	r2,	[r0],	#4
	STRCC	r2,	[r1],	#4
	BCC	%B0

1
	LDR	r1,	=|Image$$ZI$$Limit|	; Top of zero init segment
	MOV	r2,	#0

2
	CMP	r3,	r1
	STRCC	r2,	[r3],	#4
	BCC	%B2

	BL	Main
	B	.                       

;; --------------------------------------------------------------------------------------------------
;; Initialize the SPand SPSR for each mode as follows:
;;   - Corresponding stack entry => SP(Stack Pointer)
;;   - User mode with I/F clear => SPSR (Return Mode)
;; Don't use DRAM,such as stmfd,ldmfd......
;; SVCstack is initialized before
;; --------------------------------------------------------------------------------------------------

InitStacks

	mrs     r0,	cpsr
	bic     r0,	r0,	#MODEMASK
	orr     r1,	r0,	#UNDEFMODE|NOINT
	msr     cpsr_cxsf,	r1                 	;UndefMode
	ldr     sp,	=UndefStack

	orr     r1,	r0,	#ABORTMODE|NOINT
	msr     cpsr_cxsf,	r1                 	;AbortMode
	ldr     sp,	=AbortStack

	orr     r1,	r0,	#IRQMODE|NOINT
	msr     cpsr_cxsf,	r1                 	;IRQMode
	ldr     sp,	=IRQStack
        
	orr     r1,	r0,	#FIQMODE|NOINT
	msr     cpsr_cxsf,	r1                 	;FIQMode
	ldr     sp,	=FIQStack

	bic     r0,	r0,	#MODEMASK|NOINT
	orr     r1,	r0,	#SVCMODE
	msr     cpsr_cxsf,	r1                 	;SVCMode
	ldr     sp,	=SVCStack

        ;USER mode is not initialized.

        mov     pc,	lr			;The LR register may be not valid for the mode changes.

	LTORG

;; --------------------------------------------------------------------------------------------------
;; Entering Stop mode
;; --------------------------------------------------------------------------------------------------
;; void EnterPWDN(int CLKCON);
;; EnterPWDN() has to be on ROM(0~0x1fffff) for DRAM self-refresh
;; --------------------------------------------------------------------------------------------------

EnterPWDN
	mov	r10,r0

	;enter DRAM/SDRAM self refresh mode.	
	ldr	r0,	=SMRDATA1		; Load address of area 'SMRDATA'
	ldmia	r0,	{r1-r9}			; Load each word value of 'SMRDATA'
	ldr	r0,	=MEMCON0		; MEMBANK0 offset : 0x2000
	stmia	r0,	 {r1-r9}		; Store each 'SMRDATA' value to the system manager registers

        nop     ;Wait until self-refresh is issued. May not be needed.
        nop     ;If the other bus master holds the bus, ...
        nop
        nop
        nop
        nop
        nop

        ;enter POWERDN mode;
	ldr	r0,=SYSCON
	strb	r10,[r0]

        ;wait until enter STOP mode and until wake-up
	mov	r0,#0xff
0       subs    r0,r0,#1
	bne	%B0

	;exit from DRAM/SDRAM self refresh mode.	
	ldr	r0,	=SMRDATA		; Load address of area 'SMRDATA'
	ldmia	r0,	{r1-r9}			; Load each word value of 'SMRDATA'
	ldr	r0,	=MEMCON0		; MEMBANK0 offset : 0x2000
	stmia	r0,	{r1-r9}			; Store each 'SMRDATA' value to the system manager registers

	mov	pc,	lr

	LTORG


;; --------------------------------------------------------------------------------------------------
;; System Initialization Setting
;; --------------------------------------------------------------------------------------------------
;; Memory configuration has to be optimized for best performance
;; The following parameter is not optimized.
;; Memory access cycle parameter strategt
;;   - Even FP-DRAM, EDO DRAM setting has more late fetch point by half-clock
;;   - The memory setting, here, are made the safe parameters even at 25MHz
;;   - FP-DRAM parameter : 
;;   - DRAM refresh rate is for 25MHz
;; --------------------------------------------------------------------------------------------------
SyscfgDataSdram
	DCD MEMORY0_SDRAM + SYSCFG_4KB + SFR_STARTADDRESS + CACHE_ON + WRBUF_ON
	ALIGN

SyscfgDataEdoDram
	DCD MEMORY0_EDO + SYSCFG_4KB + SFR_STARTADDRESS + CACHE_ON + WRBUF_ON
	ALIGN

SMRDATA
	DCD (0x8<<21) + (0x0<<10) + TACP_5 + TACC_4 + SM_NO_16_SRAM + PMC_SINGLE + DBW_16
	DCD (0x18<<21) + (0x10<<10) + TACP_5 + TACC_3 + SM_16_SRAM + PMC_SINGLE + DBW_16
	DCD 0x0						; Bank2=Disable
	DCD 0x0						; Bank3=Disable
	DCD 0x0						; Bank4=Disable
	DCD 0x0						; Bank5=Disable
	[ DRAMTYPE = "SDRAM"
	DCD (0x200<<21) + (0x100<<10) + TRP_2 + TRC_2 + CAN_9 + DBW_16
	|	;; "DRAM"
	DCD (0x200<<21) + (0x100<<10) + TRP_3 + TRC_2 + TCAS_2 + TCP_1 + CAN_10 + DBW_16
	]
	DCD 0x0						; Bank7=Disable
	DCD (0x4f5<<1) + VSMR_1 + REFRESH_ON + TCH_2 + TCSR_1
	ALIGN

SMRDATA1
	DCD (0x2<<21) + (0x0<<10) + TACP_5 + TACC_4 + SM_NO_16_SRAM + PMC_SINGLE + DBW_16
	DCD (0x18<<21) + (0x10<<10) + TACP_5 + TACC_3 + SM_16_SRAM + PMC_SINGLE + DBW_16
	DCD 0x0						; Bank2=Disable
	DCD 0x0						; Bank3=Disable
	DCD 0x0						; Bank4=Disable
	DCD 0x0						; Bank5=Disable
	[ DRAMTYPE = "SDRAM"
	DCD (0x200<<21) + (0x100<<10) + TRP_2 + TRC_2 + CAN_9 + DBW_16
	|	;; "DRAM"
	DCD (0x200<<21) + (0x100<<10) + TRP_3 + TRC_2 + TCAS_2 + TCP_1 + CAN_10 + DBW_16
	]
	DCD 0x0						; Bank7=Disable
	DCD (0x4f5<<1) + VSMR_1 + REFRESH_OFF + TCH_2 + TCSR_1
	ALIGN

        AREA RAMData, DATA, READWRITE

        ^       (_ISR_STARTADDRESS - 0x500)
UserStack       #       256
SVCStack        #       256
UndefStack      #       256
AbortStack      #       256
IRQStack        #       256
FIQStack        #       0

        ^       _ISR_STARTADDRESS
HandleReset     #      4
HandleUndef     #      4
HandleSWI       #      4
HandlePabort    #      4
HandleDabort    #      4
HandleReserved  #      4
HandleIRQ       #      4
HandleFIQ       #      4

;; Don't use the label 'IntVectorTable',
;; because armasm.exe cann't recognize this label correctly.
;; the value is different with an address you think it may be.

IntVectorTable
HandleEINT0	#	4
HandleEINT1	#	4
HandleURX	#	4
HandleUTX	#	4
HandleUERR	#	4
HandleDMA0	#	4
HandleDMA1	#	4
HandleTOF0	#	4
HandleTMC0	#	4
HandleTOF1	#	4
HandleTMC1	#	4
HandleTOF2	#	4
HandleTMC2	#	4
HandleTOF3	#	4
HandleTMC3	#	4
HandleTOF4	#	4
HandleTMC4	#	4
HandleBT	#	4
HandleSIO0	#	4
HandleSIO1	#	4
HandleIIC	#	4
HandleRTCA	#	4
HandleRTCT	#	4
HandleTF	#	4
HandleEINT2	#	4
HandleEINT3	#	4
HandleEINT4	#	4
HandleADC	#	4
HandleEINT8	#	4
HandleEINT9	#	4
HandleEINT10	#	4
HandleEINT11	#	4
HandleUnused	#	20

	END