📄 option.a
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;****************************** OPTIONS ******************************
_RAM_STARTADDRESS EQU 0x1000000
_CPU_ASICBASE EQU 0x7ff0000
_ISR_STARTADDRESS EQU 0x1ffff00 ;GCS6:64M DRAM/SDRAM
;;; SYSCFG Configuration
STALL_ON EQU (0x1)
CACHE_ON EQU (0x1<<1)
WRBUF_ON EQU (0x1<<2)
SFR_STARTADDRESS EQU (0x7ff<<4)
MEMORY0_EDO EQU (0x2<<18)
MEMORY0_SDRAM EQU (0x3<<18)
MEMORY1_EDO EQU (0x2<<20)
MEMORY1_SDRAM EQU (0x3<<20)
;;; Cache Mode Setting
SYSCFG_0KB EQU (0x2<<15)
SYSCFG_2KB EQU (0x0<<15)
SYSCFG_4KB EQU (0x1<<15)
;;; Watch-Dog Timer Setting
WDT_DISABLE EQU (0xa5<<8)
;;; BUSWIDTH; 8,16
GBLA BUSWIDTH
BUSWIDTH SETA 16
;;; "DRAM","SDRAM"
GBLS DRAMTYPE
DRAMTYPE SETS "SDRAM"
;;; Memory Control Parameters
;;; If memory type of bank6 and bank7 is ROM/SRAM, memory control configuration of Bank0 - Bank7
;;; 31 21 20 10 9 8 7 6 4 3 2 1 0
;;; +----------------+----------------+---+-------+-----------+---+------+---+
;;; | Next Pointer | Base Pointer | X | Tacp | Tacc | SM| PMC |DBW|
;;; +----------------+----------------+---+-------+-----------+---+------+---+
;;; Bank6 - Bank7 Memory Type : MT0, MT1 in SYSCFG is 01(FP DRAM) or 10(EDO DRAM)
;;; 31 21 20 10 9 8 7 6 4 3 2 1 0
;;; +----------------+----------------+-------+---+-----------+---+------+---+
;;; | Next Pointer | Base Pointer | Trp |Trc| Tcas |Tcp| CAN |DBW|
;;; +----------------+----------------+-------+---+-----------+---+------+---+
;;; Bank6 - Bank7 Memory Type : MT0, MT1 in SYSCFG is 11(SDRAM)
;;; 31 21 20 10 9 8 7 6 4 3 2 1 0
;;; +----------------+----------------+-------+---+---------------+------+---+
;;; | Next Pointer | Base Pointer | Trp |Trc| X | CAN |DBW|
;;; +----------------+----------------+-------+---+---------------+------+---+
;;; Bank6 - Bank7 Memory Type : MT0, MT1 in SYSCFG is 11(SDRAM)
;;; 31 21 20 10 9 8 7 6 4 3 2 1 0
;;; +----+---------+----+--------------------------------+----+
;;; |Tcsr| Tch |REN | Refresh Counter |VSMW|
;;; +----+---------+----+--------------------------------+----+
;;; Next Pointer: ( End address of each bank + 1 ) / 0x10000
;;; Base Pointer: Start address of each bank / 0x10000
;;; Tacp: Number of the access cycles at page mode
;;; Tacc: Number of the access cycles
;;; SM: SRAM Memory Type 0: Normal(ROM / Flash / x8 SRAM), 1: x16 SRAM
;;; PMC: page mode configuration 00: Single, 01: 4 data, 10: 8 data, 11: 16 data
;;; DBW: Data bus width of each bank 0: 8-bit, 1: 16-bit
;;; Trp: RAS pre-charge times
;;; Trc: RAS to CAS delay
;;; Tcas: CAS pulse width
;;; Tcp: CAS pre-charge times
;;; CAN: Column address numbers
;;; Tcsr: CAS set up time for CBR refresh
;;; Tch: CAS hold time
;;; REN: Refresh enable 0: disable DRAM/SDRAM refresh/auto-refresh
;;; 1: enable DRAM/SDRAM refresh/auto-refresh
;;; Refresh counter = (2^11 + 1 - (MCLK / 15.6ua))
DBW_8 EQU 0x0
DBW_16 EQU 0x1
PMC_SINGLE EQU (0x0<<1)
PMC_4_DATA EQU (0x1<<1)
PMC_8_DATA EQU (0x2<<1)
PMC_16_DATA EQU (0x3<<1)
SM_NO_16_SRAM EQU (0x0<<3)
SM_16_SRAM EQU (0x1<<3)
TACC_2 EQU (0x1<<4)
TACC_3 EQU (0x2<<4)
TACC_4 EQU (0x3<<4)
TACC_5 EQU (0x4<<4)
TACC_6 EQU (0x5<<4)
TACC_7 EQU (0x6<<4)
TACC_10 EQU (0x7<<4)
TACP_5 EQU (0x0<<7)
TACP_2 EQU (0x1<<7)
TACP_3 EQU (0x2<<7)
TACP_4 EQU (0x3<<7)
CAN_8 EQU (0x0<<1)
CAN_9 EQU (0x1<<1)
CAN_10 EQU (0x2<<1)
CAN_11 EQU (0x3<<1)
TCP_1 EQU (0x0<<3)
TCP_2 EQU (0x1<<3)
TCAS_1 EQU (0x0<<4)
TCAS_2 EQU (0x1<<4)
TCAS_3 EQU (0x2<<4)
TCAS_4 EQU (0x3<<4)
TCAS_5 EQU (0x4<<4)
TRC_1 EQU (0x0<<7)
TRC_2 EQU (0x1<<7)
TRP_1 EQU (0x0<<8)
TRP_2 EQU (0x1<<8)
TRP_3 EQU (0x2<<8)
TRP_4 EQU (0x3<<8)
VSMR_0 EQU (0x0)
VSMR_1 EQU (0x1)
REFRESH_OFF EQU (0x0<<12)
REFRESH_ON EQU (0x1<<12)
TCH_1 EQU (0x0<<13)
TCH_2 EQU (0x1<<13)
TCH_3 EQU (0x2<<13)
TCH_4 EQU (0x3<<13)
TCH_5 EQU (0x4<<13)
TCSR_1 EQU (0x0<<16)
TCSR_2 EQU (0x1<<16)
;*********************************************************************
; Format of the Program Status Register
;
;;; 31 30 29 28 7 6 5 4 3 2 1 0
;;; +---+---+---+---+--ss--+---+---+---+---+---+---+---+---+
;;; | N | Z | C | V | | I | F | T | M4 ~ M0 |
;;; +---+---+---+---+--ss--+---+---+---+---+---+---+---+---+
;
;;; Processor Mode and Mask
;;;
;;; Mode value [M4 ~ M0]
USERMODE EQU 0x10
FIQMODE EQU 0x11
IRQMODE EQU 0x12
SVCMODE EQU 0x13
ABORTMODE EQU 0x17
UNDEFMODE EQU 0x1b
MODEMASK EQU 0x1f
;;; Value: Prohibit any interrupt
NOINT EQU 0xc0
;*********************************************************************
;;; Define special function register for Boot Program of SMDK40100
; System Control
SYSCON EQU (_CPU_ASICBASE+0xd003)
; System Manager
SYSCFG EQU (_CPU_ASICBASE+0x1000)
MEMCON0 EQU (_CPU_ASICBASE+0x2000)
MEMCON1 EQU (_CPU_ASICBASE+0x2004)
MEMCON2 EQU (_CPU_ASICBASE+0x2008)
MEMCON3 EQU (_CPU_ASICBASE+0x200c)
MEMCON4 EQU (_CPU_ASICBASE+0x2010)
MEMCON5 EQU (_CPU_ASICBASE+0x2014)
MEMCON6 EQU (_CPU_ASICBASE+0x2018)
MEMCON7 EQU (_CPU_ASICBASE+0x201c)
REFCON EQU (_CPU_ASICBASE+0x2020)
;I/O Port
PCON0 EQU (_CPU_ASICBASE+0xb010)
PCON1 EQU (_CPU_ASICBASE+0xb012)
PCON2 EQU (_CPU_ASICBASE+0xb014)
PCON3 EQU (_CPU_ASICBASE+0xb016)
PCON4 EQU (_CPU_ASICBASE+0xb018)
PCON5 EQU (_CPU_ASICBASE+0xb01c)
PCON6 EQU (_CPU_ASICBASE+0xb020)
PCON7 EQU (_CPU_ASICBASE+0xb024)
PCON8 EQU (_CPU_ASICBASE+0xb026)
PCON9 EQU (_CPU_ASICBASE+0xb027)
PUR0 EQU (_CPU_ASICBASE+0xb028)
PDR1 EQU (_CPU_ASICBASE+0xb029)
PUR2 EQU (_CPU_ASICBASE+0xb02a)
PUR3 EQU (_CPU_ASICBASE+0xb02b)
PDR4 EQU (_CPU_ASICBASE+0xb02c)
PUR5 EQU (_CPU_ASICBASE+0xb02d)
PUR6 EQU (_CPU_ASICBASE+0xb02e)
PUR7 EQU (_CPU_ASICBASE+0xb02f)
PUR8 EQU (_CPU_ASICBASE+0xb03c)
PDAT2 EQU (_CPU_ASICBASE+0xb002)
;Interrupt Control
INTPND EQU (_CPU_ASICBASE+0xc004)
INTMOD EQU (_CPU_ASICBASE+0xc000)
INTMSK EQU (_CPU_ASICBASE+0xc008)
;Watchdog timer
BTCON EQU (_CPU_ASICBASE+0xa002)
;*********************************************************************
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