pic18f4520.h

PIC18F4520 + TW8806B ucosII+net test program source

/* Definitions for CCP1CON register */
static              near bit	CCP1M0	@((unsigned)&CCP1CON*8)+0;
static              near bit	CCP1M1	@((unsigned)&CCP1CON*8)+1;
static              near bit	CCP1M2	@((unsigned)&CCP1CON*8)+2;
static              near bit	CCP1M3	@((unsigned)&CCP1CON*8)+3;
static              near bit	DC1B0	@((unsigned)&CCP1CON*8)+4;
static              near bit	DC1B1	@((unsigned)&CCP1CON*8)+5;
static              near bit	P1M0	@((unsigned)&CCP1CON*8)+6;
static              near bit	P1M1	@((unsigned)&CCP1CON*8)+7;

/* Definitions for CCP2CON register */
static              near bit	CCP2M0	@((unsigned)&CCP2CON*8)+0;
static              near bit	CCP2M1	@((unsigned)&CCP2CON*8)+1;
static              near bit	CCP2M2	@((unsigned)&CCP2CON*8)+2;
static              near bit	CCP2M3	@((unsigned)&CCP2CON*8)+3;
static              near bit	DC2B0	@((unsigned)&CCP2CON*8)+4;
static              near bit	DC2B1	@((unsigned)&CCP2CON*8)+5;

/* Definitions for BAUDCON register */
static volatile near bit	ABDEN	@((unsigned)&BAUDCON*8)+0;
static volatile near bit	WUE	@((unsigned)&BAUDCON*8)+1;
static              near bit	BRG16	@((unsigned)&BAUDCON*8)+3;
static volatile near bit	SCKP	@((unsigned)&BAUDCON*8)+4;
static volatile near bit	RCIDL	@((unsigned)&BAUDCON*8)+6;
static volatile near bit	ABDOVF	@((unsigned)&BAUDCON*8)+7;

/* Definitions for PWM1CON register */
static volatile near bit	PDC0	@((unsigned)&PWM1CON*8)+0;
static volatile near bit	PDC1	@((unsigned)&PWM1CON*8)+1;
static volatile near bit	PDC2	@((unsigned)&PWM1CON*8)+2;
static volatile near bit	PDC3	@((unsigned)&PWM1CON*8)+3;
static volatile near bit	PDC4	@((unsigned)&PWM1CON*8)+4;
static volatile near bit	PDC5	@((unsigned)&PWM1CON*8)+5;
static volatile near bit	PDC6	@((unsigned)&PWM1CON*8)+6;
static volatile near bit	PRSEN	@((unsigned)&PWM1CON*8)+7;

/* Definitions for ECCP1AS register */
static              near bit	PSSBD0	@((unsigned)&ECCP1AS*8)+0;
static              near bit	PSSBD1	@((unsigned)&ECCP1AS*8)+1;
static              near bit	PSSAC0	@((unsigned)&ECCP1AS*8)+2;
static              near bit	PSSAC1	@((unsigned)&ECCP1AS*8)+3;
static              near bit	ECCPAS0	@((unsigned)&ECCP1AS*8)+4;
static              near bit	ECCPAS1	@((unsigned)&ECCP1AS*8)+5;
static              near bit	ECCPAS2	@((unsigned)&ECCP1AS*8)+6;
static volatile near bit	ECCPASE	@((unsigned)&ECCP1AS*8)+7;

/* Definitions for CVRCON register */
static              near bit	CVR0	@((unsigned)&CVRCON*8)+0;
static              near bit	CVR1	@((unsigned)&CVRCON*8)+1;
static              near bit	CVR2	@((unsigned)&CVRCON*8)+2;
static              near bit	CVR3	@((unsigned)&CVRCON*8)+3;
static              near bit	CVRSS	@((unsigned)&CVRCON*8)+4;
static              near bit	CVRR	@((unsigned)&CVRCON*8)+5;
static              near bit	CVROE	@((unsigned)&CVRCON*8)+6;
static              near bit	CVREN	@((unsigned)&CVRCON*8)+7;

/* Definitions for CMCON register */
static              near bit	CM0	@((unsigned)&CMCON*8)+0;
static              near bit	CM1	@((unsigned)&CMCON*8)+1;
static              near bit	CM2	@((unsigned)&CMCON*8)+2;
static              near bit	CIS	@((unsigned)&CMCON*8)+3;
static              near bit	C1INV	@((unsigned)&CMCON*8)+4;
static              near bit	C2INV	@((unsigned)&CMCON*8)+5;
static volatile near bit	C1OUT	@((unsigned)&CMCON*8)+6;
static volatile near bit	C2OUT	@((unsigned)&CMCON*8)+7;

/* Definitions for T3CON register */
static              near bit	TMR3ON	@((unsigned)&T3CON*8)+0;
static              near bit	TMR3CS	@((unsigned)&T3CON*8)+1;
static              near bit	T3SYNC	@((unsigned)&T3CON*8)+2;
static              near bit	T3CCP1	@((unsigned)&T3CON*8)+3;
static              near bit	T3CKPS0	@((unsigned)&T3CON*8)+4;
static              near bit	T3CKPS1	@((unsigned)&T3CON*8)+5;
static              near bit	T3CCP2	@((unsigned)&T3CON*8)+6;
static              near bit	T3RD16	@((unsigned)&T3CON*8)+7;

/* Definitions for TXSTA register */
static volatile near bit	TX9D	@((unsigned)&TXSTA*8)+0;
static volatile near bit	TRMT	@((unsigned)&TXSTA*8)+1;
static              near bit	BRGH	@((unsigned)&TXSTA*8)+2;
static              near bit	SENDB	@((unsigned)&TXSTA*8)+3;
static              near bit	SYNC	@((unsigned)&TXSTA*8)+4;
static              near bit	TXEN	@((unsigned)&TXSTA*8)+5;
static              near bit	TX9	@((unsigned)&TXSTA*8)+6;
static              near bit	CSRC	@((unsigned)&TXSTA*8)+7;

/* Definitions for RCSTA register */
static volatile near bit	RX9D	@((unsigned)&RCSTA*8)+0;
static volatile near bit	OERR	@((unsigned)&RCSTA*8)+1;
static volatile near bit	FERR	@((unsigned)&RCSTA*8)+2;
static              near bit	ADDEN	@((unsigned)&RCSTA*8)+3;
static              near bit	CREN	@((unsigned)&RCSTA*8)+4;
static              near bit	SREN	@((unsigned)&RCSTA*8)+5;
static              near bit	RX9	@((unsigned)&RCSTA*8)+6;
static              near bit	SPEN	@((unsigned)&RCSTA*8)+7;

/* Definitions for EECON1 register */
static volatile near bit	RD	@((unsigned)&EECON1*8)+0;
static volatile near bit	WR	@((unsigned)&EECON1*8)+1;
static              near bit	WREN	@((unsigned)&EECON1*8)+2;
static volatile near bit	WRERR	@((unsigned)&EECON1*8)+3;
static volatile near bit	FREE	@((unsigned)&EECON1*8)+4;
static              near bit	CFGS	@((unsigned)&EECON1*8)+6;
static              near bit	EEPGD	@((unsigned)&EECON1*8)+7;

/* Definitions for IPR2 register */
static near bit		CCP2IP	@((unsigned)&IPR2*8)+0;
static near bit		TMR3IP	@((unsigned)&IPR2*8)+1;
static near bit		HLVDIP	@((unsigned)&IPR2*8)+2;
static near bit		BCLIP	@((unsigned)&IPR2*8)+3;
static near bit		EEIP	@((unsigned)&IPR2*8)+4;
static near bit		CMIP	@((unsigned)&IPR2*8)+6;
static near bit		OSCFIP	@((unsigned)&IPR2*8)+7;

/* Definitions for PIR2 register */
static volatile near bit	CCP2IF	@((unsigned)&PIR2*8)+0;
static volatile near bit	TMR3IF	@((unsigned)&PIR2*8)+1;
static volatile near bit	HLVDIF	@((unsigned)&PIR2*8)+2;
static volatile near bit	BCLIF	@((unsigned)&PIR2*8)+3;
static volatile near bit	EEIF	@((unsigned)&PIR2*8)+4;
static volatile near bit	CMIF	@((unsigned)&PIR2*8)+6;
static volatile near bit	OSCFIF	@((unsigned)&PIR2*8)+7;

/* Definitions for PIE2 register */
static near bit		CCP2IE	@((unsigned)&PIE2*8)+0;
static near bit		TMR3IE	@((unsigned)&PIE2*8)+1;
static near bit		HLVDIE	@((unsigned)&PIE2*8)+2;
static near bit		BCLIE	@((unsigned)&PIE2*8)+3;
static near bit		EEIE	@((unsigned)&PIE2*8)+4;
static near bit		CMIE	@((unsigned)&PIE2*8)+6;
static near bit		OSCFIE	@((unsigned)&PIE2*8)+7;

/* Definitions for IPR1 register */
static near bit		TMR1IP	@((unsigned)&IPR1*8)+0;
static near bit		TMR2IP	@((unsigned)&IPR1*8)+1;
static near bit		CCP1IP	@((unsigned)&IPR1*8)+2;
static near bit		SSPIP	@((unsigned)&IPR1*8)+3;
static near bit		TXIP	@((unsigned)&IPR1*8)+4;
static near bit		RCIP	@((unsigned)&IPR1*8)+5;
static near bit		ADIP	@((unsigned)&IPR1*8)+6;
static near bit		PSPIP	@((unsigned)&IPR1*8)+7;

/* Definitions for PIR1 register */
static volatile near bit	TMR1IF	@((unsigned)&PIR1*8)+0;
static volatile near bit	TMR2IF	@((unsigned)&PIR1*8)+1;
static volatile near bit	CCP1IF	@((unsigned)&PIR1*8)+2;
static volatile near bit	SSPIF	@((unsigned)&PIR1*8)+3;
static volatile near bit	TXIF	@((unsigned)&PIR1*8)+4;
static volatile near bit	RCIF	@((unsigned)&PIR1*8)+5;
static volatile near bit	ADIF	@((unsigned)&PIR1*8)+6;
static volatile near bit	PSPIF	@((unsigned)&PIR1*8)+7;

/* Definitions for PIE1 register */
static near bit		TMR1IE	@((unsigned)&PIE1*8)+0;
static near bit		TMR2IE	@((unsigned)&PIE1*8)+1;
static near bit		CCP1IE	@((unsigned)&PIE1*8)+2;
static near bit		SSPIE	@((unsigned)&PIE1*8)+3;
static near bit		TXIE	@((unsigned)&PIE1*8)+4;
static near bit		RCIE	@((unsigned)&PIE1*8)+5;
static near bit		ADIE	@((unsigned)&PIE1*8)+6;
static near bit		PSPIE	@((unsigned)&PIE1*8)+7;

/* Definitions for PORTE register */
static volatile near bit	RE0	@((unsigned)&PORTE*8)+0;
static volatile near bit	RE1	@((unsigned)&PORTE*8)+1;
static volatile near bit	RE2	@((unsigned)&PORTE*8)+2;
static volatile near bit	RE3	@((unsigned)&PORTE*8)+3;

/* Definitions for PORTD register */
static volatile near bit	RD0	@((unsigned)&PORTD*8)+0;
static volatile near bit	RD1	@((unsigned)&PORTD*8)+1;
static volatile near bit	RD2	@((unsigned)&PORTD*8)+2;
static volatile near bit	RD3	@((unsigned)&PORTD*8)+3;
static volatile near bit	RD4	@((unsigned)&PORTD*8)+4;
static volatile near bit	RD5	@((unsigned)&PORTD*8)+5;
static volatile near bit	RD6	@((unsigned)&PORTD*8)+6;
static volatile near bit	RD7	@((unsigned)&PORTD*8)+7;

/* Definitions for PORTC register */
static volatile near bit	RC0	@((unsigned)&PORTC*8)+0;
static volatile near bit	RC1	@((unsigned)&PORTC*8)+1;
static volatile near bit	RC2	@((unsigned)&PORTC*8)+2;
static volatile near bit	RC3	@((unsigned)&PORTC*8)+3;
static volatile near bit	RC4	@((unsigned)&PORTC*8)+4;
static volatile near bit	RC5	@((unsigned)&PORTC*8)+5;
static volatile near bit	RC6	@((unsigned)&PORTC*8)+6;
static volatile near bit	RC7	@((unsigned)&PORTC*8)+7;

/* Definitions for PORTB register */
static volatile near bit	RB0	@((unsigned)&PORTB*8)+0;
static volatile near bit	RB1	@((unsigned)&PORTB*8)+1;
static volatile near bit	RB2	@((unsigned)&PORTB*8)+2;
static volatile near bit	RB3	@((unsigned)&PORTB*8)+3;
static volatile near bit	RB4	@((unsigned)&PORTB*8)+4;
static volatile near bit	RB5	@((unsigned)&PORTB*8)+5;
static volatile near bit	RB6	@((unsigned)&PORTB*8)+6;
static volatile near bit	RB7	@((unsigned)&PORTB*8)+7;

/* Definitions for PORTA register */
static volatile near bit	RA0	@((unsigned)&PORTA*8)+0;
static volatile near bit	RA1	@((unsigned)&PORTA*8)+1;
static volatile near bit	RA2	@((unsigned)&PORTA*8)+2;
static volatile near bit	RA3	@((unsigned)&PORTA*8)+3;
static volatile near bit	RA4	@((unsigned)&PORTA*8)+4;
static volatile near bit	RA5	@((unsigned)&PORTA*8)+5;
static volatile near bit	RA6	@((unsigned)&PORTA*8)+6;
static volatile near bit	RA7	@((unsigned)&PORTA*8)+7;

#define 	Clear_Watchdog	asm("CLRWDT")	//Clear Watchdog Timer
#define	DisableInterrupts	GIE = 0		//Disable Global Interrupt
#define	EnableInterrupts	GIE = 1		//Enables Global Interrupt

#define	ROMSIZE 		32768
#define	EEPROM_SIZE 	256

#define	___mkstr1(x)	#x
#define	___mkstr(x)	___mkstr1(x)
#define	__CONFIG(n, x)	asm("\tpsect config,class=CONFIG");\
			asm("global config_word" ___mkstr(n)); \
			asm("\torg ("___mkstr(n)"-1)*2"); \
			asm("config_word" ___mkstr(n)":"); \
			asm("\tdw "___mkstr(x))

#define	__EEPROM_DATA(a, b, c, d, e, f, g, h) \
			 asm("\tpsect eeprom_data,class=EEDATA"); \
			 asm("\tdb\t" ___mkstr(a) "," ___mkstr(b) "," ___mkstr(c) "," ___mkstr(d) "," \
				      ___mkstr(e) "," ___mkstr(f) "," ___mkstr(g) "," ___mkstr(h))
				      
/*===============================================================================================
**		Copy Right Copyright WOORY⑩ Industrial Company Limited. 1989-2007
===============================================================================================*/