sha256_sha512_dataio.v

Verilog实现的SHA256/SHA512算法

 

module     sha256_sha512_dataio(
			    clk,    
                            rst_n,    
                            sha256_sw_rst,
			    sha512_sw_rst,
			    
			    sha256_load_A2H,
			    sha256_load_data,
			    sha512_load_A2H,
			    sha512_load_data,
			    sha256_sha512_datain,
			    //sha256_start,
			    //sha512_start,
			    sha256_data_return,
			    sha512_data_return,
			    
			   
			    sha256_dataout,
			    sha512_dataout,
			    
                            a_temp,
                            b_temp,
                            c_temp,
                            d_temp,
                            e_temp,
                            f_temp,
                            g_temp,
                            h_temp,
                             
                            cal_ready,  
                           
                            reg_a,
                            reg_b,
                            reg_c,
                            reg_d,
                            reg_e,
                            reg_f,
                            reg_g,
                            reg_h,
                          
                            wt_data,
                            wt_data_en  
                           ); 
                             
//`include  "parameter.v" 

input  clk          ;    //system clock form chip pin.                                                                                           
input  rst_n            ;    //reset signal from chip pin, it is a async and low active.                                                             
input  sha256_sw_rst;                                                                     
input  sha512_sw_rst;                                                //The most high bit is always "1", and in this module it don't be sent.                                                 
input  sha256_load_A2H;
input  sha256_load_data;
input  sha512_load_A2H;
input  sha512_load_data;
input [31:0] sha256_sha512_datain;
//input  sha256_start;
//input  sha512_start;
input  sha256_data_return;
input  sha512_data_return;

output [31:0] sha256_dataout;
output [31:0] sha512_dataout;           

input[63:0]                a_temp           ;    //a_temp from the alu module, it is the final "a" caculation result              
input[63:0]                b_temp           ;    //b_temp from the alu module, it is the final "b" caculation result               
input[63:0]                c_temp           ;    //c_temp from the alu module, it is the final "c" caculation result               
input[63:0]                d_temp           ;    //d_temp from the alu module, it is the final "d" caculation result               
input[63:0]                e_temp           ;    //e_temp from the alu module, it is the final "e" caculation result               
input[63:0]                f_temp           ;    //c_temp from the alu module, it is the final "c" caculation result               
input[63:0]                g_temp           ;    //d_temp from the alu module, it is the final "d" caculation result               
input[63:0]                h_temp           ;    //e_temp from the alu module, it is the final "e" caculation result               


input                      cal_ready       ;

output[63:0]               reg_a       ;    //temp store the "A", 1, for transfer to "a" 2, for final 32bit adder
output[63:0]               reg_b       ;    //temp store the "B", 1, for transfer to "b" 2, for final 32bit adder
output[63:0]               reg_c       ;    //temp store the "C", 1, for transfer to "c" 2, for final 32bit adder
output[63:0]               reg_d       ;    //temp store the "D", 1, for transfer to "d" 2, for final 32bit adder
output[63:0]               reg_e       ;    //temp store the "E", 1, for transfer to "e" 2, for final 32bit adder
output[63:0]               reg_f       ;    //temp store the "C", 1, for transfer to "c" 2, for final 32bit adder
output[63:0]               reg_g       ;    //temp store the "D", 1, for transfer to "d" 2, for final 32bit adder
output[63:0]               reg_h       ;    //temp store the "E", 1, for transfer to "e" 2, for final 32bit adder

output[63:0]               wt_data          ;    //output the wt data;
output                     wt_data_en       ;    //enable the wt data;


		


reg[63:0]                  reg_a      ;      //"A,B,C,D,E,WT" reg
reg[63:0]                  reg_b      ;
reg[63:0]                  reg_c      ;
reg[63:0]                  reg_d      ;
reg[63:0]                  reg_e      ;
reg[63:0]                  reg_f      ;
reg[63:0]                  reg_g      ;
reg[63:0]                  reg_h      ;
reg[63:0]                  wt_data         ;
reg                        wt_data_en      ;


reg cnt_load;


assign sha256_dataout =  reg_h[63:32];
assign sha512_dataout = reg_h[31:0];

always @ (posedge clk or negedge rst_n)begin
  if(!rst_n) begin 
     wt_data <= 64'd0;
     wt_data_en <= 1'b0;
  end
  else if(sha256_sw_rst|sha512_sw_rst)begin
     wt_data <= 64'd0;
     wt_data_en <= 1'b0;
  end
  else begin
    if(sha256_load_data|sha512_load_data)begin
       if(sha256_load_data) begin
          wt_data <= {sha256_sha512_datain,32'd0};
          wt_data_en <= 1'b1;
        end       
       if(sha512_load_data) begin
          wt_data <= {sha256_sha512_datain,wt_data[63:32]};
         if(cnt_load) wt_data_en <= 1'b1;
       end
    end
    else begin
       wt_data_en <= 1'b0;
    end
  end
end


always @ (posedge clk or negedge rst_n)begin
  if(!rst_n) begin 
    reg_a <= {32'h6a09e667,32'd0};
    reg_b <= {32'hbb67ae85,32'd0};
    reg_c <= {32'h3c6ef372,32'd0};
    reg_d <= {32'ha54ff53a,32'd0};
    reg_e <= {32'h510e527f,32'd0};
    reg_f <= {32'h9b05688c,32'd0};
    reg_g <= {32'h1f83d9ab,32'd0};
    reg_h <= {32'h5be0cd19,32'd0};       

  end
  else if(sha256_sw_rst)begin
    reg_a <= {32'h6a09e667,32'd0};
    reg_b <= {32'hbb67ae85,32'd0};
    reg_c <= {32'h3c6ef372,32'd0};
    reg_d <= {32'ha54ff53a,32'd0};
    reg_e <= {32'h510e527f,32'd0};
    reg_f <= {32'h9b05688c,32'd0};
    reg_g <= {32'h1f83d9ab,32'd0};
    reg_h <= {32'h5be0cd19,32'd0};            
  end  
  else if(sha512_sw_rst)begin
    reg_a <= 64'h6a09e667f3bcc908;
    reg_b <= 64'hbb67ae8584caa73b;
    reg_c <= 64'h3c6ef372fe94f82b;
    reg_d <= 64'ha54ff53a5f1d36f1;
    reg_e <= 64'h510e527fade682d1;
    reg_f <= 64'h9b05688c2b3e6c1f;
    reg_g <= 64'h1f83d9abfb41bd6b;
    reg_h <= 64'h5be0cd19137e2179;
  end  
  else begin
    if(sha256_load_A2H|sha256_data_return)begin      
        reg_b <= reg_a;
        reg_c <= reg_b;
        reg_d <= reg_c;
        reg_e <= reg_d;
        reg_f <= reg_e;
        reg_g <= reg_f;
        reg_h <= reg_g;
        if(sha256_load_A2H)
           reg_a <= {sha256_sha512_datain,32'd0}; 
        if(sha256_data_return)
           reg_a <= reg_h;
    end    
    if(sha512_load_A2H)begin
          reg_a <= {sha256_sha512_datain,reg_a[63:32]};
	  if(~cnt_load)begin
	     reg_b <= reg_a;
             reg_c <= reg_b;
             reg_d <= reg_c;
             reg_e <= reg_d;
             reg_f <= reg_e;
             reg_g <= reg_f;
             reg_h <= reg_g;
	  end	
    end 
    if(sha512_data_return)begin	  
          if(cnt_load) begin
            reg_b <= reg_a;
            reg_c <= reg_b;
            reg_d <= reg_c;
            reg_e <= reg_d;
            reg_f <= reg_e;
            reg_g <= reg_f;
            reg_h <= reg_g;
          end
	  else begin
	    reg_h <= {reg_h[31:0],reg_h[63:32]};
	  end
    end	         
    if(cal_ready)begin
       reg_a <= reg_a + a_temp;
       reg_b <= reg_b + b_temp;
       reg_c <= reg_c + c_temp;
       reg_d <= reg_d + d_temp;
       reg_e <= reg_e + e_temp;
       reg_f <= reg_f + f_temp;
       reg_g <= reg_g + g_temp;
       reg_h <= reg_h + h_temp;
    end
  end
end

always @ (posedge clk or negedge rst_n)begin
  if(!rst_n) cnt_load <= 1'b0;
  else if(sha512_load_A2H|sha512_load_data|sha512_data_return)begin
     cnt_load <= cnt_load + 1'b1;
  end
end

                         
endmodule