sha256_sha512_wt.v

Verilog实现的SHA256/SHA512算法

module   sha256_sha512_wt(
                             clk,
                             rst_n,
			     sha256_sw_rst,
			     sha512_sw_rst,
                             wt_data,
                             wt_data_en,
                             wt_request,
                             sha256_start,
			     sha512_start,
                         
                             
// output                          
                             wt_data_out      ,
                             wt_dataout_en    ); 


input    clk;
input    rst_n; 
input    sha256_sw_rst;
input    sha512_sw_rst;
input    sha256_start;
input    sha512_start;   
                         
input[63:0]              wt_data        ;
input                    wt_data_en     ;

input                    wt_request     ;

output[63:0]             wt_data_out    ;
output                   wt_dataout_en  ;


reg [63:0] 		 wt_data_out;
reg                      wt_dataout_en  ;
reg[1023:0]              wt_register    ;
wire[63:0]               wt_512_temp        ;
wire[63:0]               wt_256_temp        ;

// data input 
always@(posedge clk or negedge rst_n)
begin
    if(!rst_n)
	wt_register  <= 1024'd0;
    else if(sha256_sw_rst|sha512_sw_rst)
    	wt_register  <= 1024'd0;
    else begin
      if(wt_data_en) wt_register <= {wt_data,wt_register[1023:64]};
      if(wt_request) begin
         wt_register[1023:64] <= wt_register[959:0];
         if(sha256_start)
	        wt_register[63:0] <= wt_256_temp;			
	 else
	        wt_register[63:0] <= wt_512_temp;
      end
    end
    
end

//wire [63:0] debug_t1 = wt_register[63:0];

// data shift
wire [63:0] wt_256_1 = sha256_shr1(wt_register[127:64]);
wire [31:0] wt_256_2 = wt_register[447:416];
wire [63:0] wt_256_3 = sha256_shr0(wt_register[959:896]);
wire [31:0] wt_256_4 = wt_register[1023:992];
wire [31:0] wt_256_5 = wt_256_1[63:32] + wt_256_2 + wt_256_3[63:32] + wt_256_4;

assign wt_512_temp = sha512_shr1(wt_register[127:64]) + wt_register[447:384] + sha512_shr0(wt_register[959:896]) + wt_register[1023:960];
assign wt_256_temp = {wt_256_5,32'd0};


// data output 
always@(posedge clk or negedge rst_n )
     if(!rst_n)
       begin
           wt_data_out  <= 64'd0;
           wt_dataout_en<= 1'b0;
       end
    else if(sha256_sw_rst|sha512_sw_rst)
       begin
           wt_data_out  <= 64'd0;
           wt_dataout_en<= 1'b0;
       end
     else if(wt_request)
       begin 
           wt_data_out   <= wt_register[1023:960];
           wt_dataout_en <= 1'b1;
       end
     else
       begin 
           wt_data_out  <= 64'd0;
           wt_dataout_en<= 1'b0;
       end

 
// -------------------------------------------
// 	-- function realize --
// -------------------------------------------
function [63:0] sha512_shr0;
input [63:0] x;
reg [63:0] rot1;
reg [63:0] rot8;
reg [63:0] shr7;
begin
	rot1 = {x[0],x[63:1]};
	rot8 = {x[7:0],x[63:8]};
//	shr7 = {{7{x[63]}},x[63:7]};
	shr7 = {{7'd0},x[63:7]};
	sha512_shr0 = rot1^rot8^shr7;
end
endfunction
//		--------------
function [63:0] sha512_shr1;
input [63:0] x;
reg [63:0] rot19;
reg [63:0] rot61;
reg [63:0] shr6;
begin
	rot19 = {x[18:0],x[63:19]};
	rot61 = {x[60:0],x[63:61]};
//	shr6 = {{6{x[63]}},x[63:6]}; 
	shr6 = {{6'd0},x[63:6]};
	sha512_shr1 = rot19^rot61^shr6;
end
endfunction
//		--------------
function [63:0] sha256_shr0;
input [63:0] x;
reg [31:0] rot7;
reg [31:0] rot18;
reg [31:0] shr3;
reg [31:0] y;
begin
	rot7 = {x[38:32],x[63:39]};
	rot18 = {x[49:32],x[63:50]};
	shr3 = {{3'd0},x[63:35]};
	y = rot7^rot18^shr3;
	sha256_shr0 = {y,32'd0};
end
endfunction
//		--------------
function [63:0] sha256_shr1;
input [63:0] x;
reg [31:0] rot17;
reg [31:0] rot19;
reg [31:0] shr10;
reg [31:0] y;
begin
	rot17 = {x[48:32],x[63:49]};
	rot19 = {x[50:32],x[63:51]};
	shr10 = {{10'd0},x[63:42]};
	y =  rot19^rot17^shr10;
	sha256_shr1 = {y,32'd0};
end
endfunction

       
endmodule