motorcombustion.tan.qmsg

State Machine of Motor implemented in VHDL.

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clock register register proximoestado.posicioninicial proximoestado.admision 500.0 MHz Internal " "Info: Clock \"clock\" Internal fmax is restricted to 500.0 MHz between source register \"proximoestado.posicioninicial\" and destination register \"proximoestado.admision\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.0 ns " "Info: fmax restricted to clock pin edge rate 2.0 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.560 ns + Longest register register " "Info: + Longest register to register delay is 0.560 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns proximoestado.posicioninicial 1 REG LCFF_X31_Y26_N3 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X31_Y26_N3; Fanout = 1; REG Node = 'proximoestado.posicioninicial'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { proximoestado.posicioninicial } "NODE_NAME" } } { "motorcombustion.vhd" "" { Text "C:/Documents and Settings/Alejandro Aguilar/My Documents/UNIVALLE/Noveno semestre/Prototipado Rapido y VHDL/Tarea2 VHDL/motorcombustion/motorcombustion.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.352 ns) + CELL(0.053 ns) 0.405 ns proximoestado.admision~8 2 COMB LCCOMB_X31_Y26_N0 1 " "Info: 2: + IC(0.352 ns) + CELL(0.053 ns) = 0.405 ns; Loc. = LCCOMB_X31_Y26_N0; Fanout = 1; COMB Node = 'proximoestado.admision~8'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.405 ns" { proximoestado.posicioninicial proximoestado.admision~8 } "NODE_NAME" } } { "motorcombustion.vhd" "" { Text "C:/Documents and Settings/Alejandro Aguilar/My Documents/UNIVALLE/Noveno semestre/Prototipado Rapido y VHDL/Tarea2 VHDL/motorcombustion/motorcombustion.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.155 ns) 0.560 ns proximoestado.admision 3 REG LCFF_X31_Y26_N1 2 " "Info: 3: + IC(0.000 ns) + CELL(0.155 ns) = 0.560 ns; Loc. = LCFF_X31_Y26_N1; Fanout = 2; REG Node = 'proximoestado.admision'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.155 ns" { proximoestado.admision~8 proximoestado.admision } "NODE_NAME" } } { "motorcombustion.vhd" "" { Text "C:/Documents and Settings/Alejandro Aguilar/My Documents/UNIVALLE/Noveno semestre/Prototipado Rapido y VHDL/Tarea2 VHDL/motorcombustion/motorcombustion.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.208 ns ( 37.14 % ) " "Info: Total cell delay = 0.208 ns ( 37.14 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.352 ns ( 62.86 % ) " "Info: Total interconnect delay = 0.352 ns ( 62.86 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.560 ns" { proximoestado.posicioninicial proximoestado.admision~8 proximoestado.admision } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "0.560 ns" { proximoestado.posicioninicial proximoestado.admision~8 proximoestado.admision } { 0.000ns 0.352ns 0.000ns } { 0.000ns 0.053ns 0.155ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 2.493 ns + Shortest register " "Info: + Shortest clock path from clock \"clock\" to destination register is 2.493 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clock 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clock'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "motorcombustion.vhd" "" { Text "C:/Documents and Settings/Alejandro Aguilar/My Documents/UNIVALLE/Noveno semestre/Prototipado Rapido y VHDL/Tarea2 VHDL/motorcombustion/motorcombustion.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns clock~clkctrl 2 COMB CLKCTRL_G3 6 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 6; COMB Node = 'clock~clkctrl'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { clock clock~clkctrl } "NODE_NAME" } } { "motorcombustion.vhd" "" { Text "C:/Documents and Settings/Alejandro Aguilar/My Documents/UNIVALLE/Noveno semestre/Prototipado Rapido y VHDL/Tarea2 VHDL/motorcombustion/motorcombustion.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.678 ns) + CELL(0.618 ns) 2.493 ns proximoestado.admision 3 REG LCFF_X31_Y26_N1 2 " "Info: 3: + IC(0.678 ns) + CELL(0.618 ns) = 2.493 ns; Loc. = LCFF_X31_Y26_N1; Fanout = 2; REG Node = 'proximoestado.admision'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.296 ns" { clock~clkctrl proximoestado.admision } "NODE_NAME" } } { "motorcombustion.vhd" "" { Text "C:/Documents and Settings/Alejandro Aguilar/My Documents/UNIVALLE/Noveno semestre/Prototipado Rapido y VHDL/Tarea2 VHDL/motorcombustion/motorcombustion.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 59.05 % ) " "Info: Total cell delay = 1.472 ns ( 59.05 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.021 ns ( 40.95 % ) " "Info: Total interconnect delay = 1.021 ns ( 40.95 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.493 ns" { clock clock~clkctrl proximoestado.admision } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.493 ns" { clock clock~combout clock~clkctrl proximoestado.admision } { 0.000ns 0.000ns 0.343ns 0.678ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 2.493 ns - Longest register " "Info: - Longest clock path from clock \"clock\" to source register is 2.493 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clock 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clock'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "motorcombustion.vhd" "" { Text "C:/Documents and Settings/Alejandro Aguilar/My Documents/UNIVALLE/Noveno semestre/Prototipado Rapido y VHDL/Tarea2 VHDL/motorcombustion/motorcombustion.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns clock~clkctrl 2 COMB CLKCTRL_G3 6 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 6; COMB Node = 'clock~clkctrl'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { clock clock~clkctrl } "NODE_NAME" } } { "motorcombustion.vhd" "" { Text "C:/Documents and Settings/Alejandro Aguilar/My Documents/UNIVALLE/Noveno semestre/Prototipado Rapido y VHDL/Tarea2 VHDL/motorcombustion/motorcombustion.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.678 ns) + CELL(0.618 ns) 2.493 ns proximoestado.posicioninicial 3 REG LCFF_X31_Y26_N3 1 " "Info: 3: + IC(0.678 ns) + CELL(0.618 ns) = 2.493 ns; Loc. = LCFF_X31_Y26_N3; Fanout = 1; REG Node = 'proximoestado.posicioninicial'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.296 ns" { clock~clkctrl proximoestado.posicioninicial } "NODE_NAME" } } { "motorcombustion.vhd" "" { Text "C:/Documents and Settings/Alejandro Aguilar/My Documents/UNIVALLE/Noveno semestre/Prototipado Rapido y VHDL/Tarea2 VHDL/motorcombustion/motorcombustion.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 59.05 % ) " "Info: Total cell delay = 1.472 ns ( 59.05 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.021 ns ( 40.95 % ) " "Info: Total interconnect delay = 1.021 ns ( 40.95 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.493 ns" { clock clock~clkctrl proximoestado.posicioninicial } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.493 ns" { clock clock~combout clock~clkctrl proximoestado.posicioninicial } { 0.000ns 0.000ns 0.343ns 0.678ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.493 ns" { clock clock~clkctrl proximoestado.admision } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.493 ns" { clock clock~combout clock~clkctrl proximoestado.admision } { 0.000ns 0.000ns 0.343ns 0.678ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.493 ns" { clock clock~clkctrl proximoestado.posicioninicial } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.493 ns" { clock clock~combout clock~clkctrl proximoestado.posicioninicial } { 0.000ns 0.000ns 0.343ns 0.678ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.094 ns + " "Info: + Micro clock to output delay of source is 0.094 ns" {  } { { "motorcombustion.vhd" "" { Text "C:/Documents and Settings/Alejandro Aguilar/My Documents/UNIVALLE/Noveno semestre/Prototipado Rapido y VHDL/Tarea2 VHDL/motorcombustion/motorcombustion.vhd" 18 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.090 ns + " "Info: + Micro setup delay of destination is 0.090 ns" {  } { { "motorcombustion.vhd" "" { Text "C:/Documents and Settings/Alejandro Aguilar/My Documents/UNIVALLE/Noveno semestre/Prototipado Rapido y VHDL/Tarea2 VHDL/motorcombustion/motorcombustion.vhd" 18 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.560 ns" { proximoestado.posicioninicial proximoestado.admision~8 proximoestado.admision } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "0.560 ns" { proximoestado.posicioninicial proximoestado.admision~8 proximoestado.admision } { 0.000ns 0.352ns 0.000ns } { 0.000ns 0.053ns 0.155ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.493 ns" { clock clock~clkctrl proximoestado.admision } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.493 ns" { clock clock~combout clock~clkctrl proximoestado.admision } { 0.000ns 0.000ns 0.343ns 0.678ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.493 ns" { clock clock~clkctrl proximoestado.posicioninicial } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.493 ns" { clock clock~combout clock~clkctrl proximoestado.posicioninicial } { 0.000ns 0.000ns 0.343ns 0.678ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { proximoestado.admision } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { proximoestado.admision } {  } {  } "" } } { "motorcombustion.vhd" "" { Text "C:/Documents and Settings/Alejandro Aguilar/My Documents/UNIVALLE/Noveno semestre/Prototipado Rapido y VHDL/Tarea2 VHDL/motorcombustion/motorcombustion.vhd" 18 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clock salida\[2\] proximoestado.admision 5.609 ns register " "Info: tco from clock \"clock\" to destination pin \"salida\[2\]\" through register \"proximoestado.admision\" is 5.609 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 2.493 ns + Longest register " "Info: + Longest clock path from clock \"clock\" to source register is 2.493 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clock 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clock'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "motorcombustion.vhd" "" { Text "C:/Documents and Settings/Alejandro Aguilar/My Documents/UNIVALLE/Noveno semestre/Prototipado Rapido y VHDL/Tarea2 VHDL/motorcombustion/motorcombustion.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns clock~clkctrl 2 COMB CLKCTRL_G3 6 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 6; COMB Node = 'clock~clkctrl'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { clock clock~clkctrl } "NODE_NAME" } } { "motorcombustion.vhd" "" { Text "C:/Documents and Settings/Alejandro Aguilar/My Documents/UNIVALLE/Noveno semestre/Prototipado Rapido y VHDL/Tarea2 VHDL/motorcombustion/motorcombustion.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.678 ns) + CELL(0.618 ns) 2.493 ns proximoestado.admision 3 REG LCFF_X31_Y26_N1 2 " "Info: 3: + IC(0.678 ns) + CELL(0.618 ns) = 2.493 ns; Loc. = LCFF_X31_Y26_N1; Fanout = 2; REG Node = 'proximoestado.admision'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.296 ns" { clock~clkctrl proximoestado.admision } "NODE_NAME" } } { "motorcombustion.vhd" "" { Text "C:/Documents and Settings/Alejandro Aguilar/My Documents/UNIVALLE/Noveno semestre/Prototipado Rapido y VHDL/Tarea2 VHDL/motorcombustion/motorcombustion.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 59.05 % ) " "Info: Total cell delay = 1.472 ns ( 59.05 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.021 ns ( 40.95 % ) " "Info: Total interconnect delay = 1.021 ns ( 40.95 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.493 ns" { clock clock~clkctrl proximoestado.admision } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.493 ns" { clock clock~combout clock~clkctrl proximoestado.admision } { 0.000ns 0.000ns 0.343ns 0.678ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.094 ns + " "Info: + Micro clock to output delay of source is 0.094 ns" {  } { { "motorcombustion.vhd" "" { Text "C:/Documents and Settings/Alejandro Aguilar/My Documents/UNIVALLE/Noveno semestre/Prototipado Rapido y VHDL/Tarea2 VHDL/motorcombustion/motorcombustion.vhd" 18 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.022 ns + Longest register pin " "Info: + Longest register to pin delay is 3.022 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns proximoestado.admision 1 REG LCFF_X31_Y26_N1 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X31_Y26_N1; Fanout = 2; REG Node = 'proximoestado.admision'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { proximoestado.admision } "NODE_NAME" } } { "motorcombustion.vhd" "" { Text "C:/Documents and Settings/Alejandro Aguilar/My Documents/UNIVALLE/Noveno semestre/Prototipado Rapido y VHDL/Tarea2 VHDL/motorcombustion/motorcombustion.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.878 ns) + CELL(2.144 ns) 3.022 ns salida\[2\] 2 PIN PIN_E3 0 " "Info: 2: + IC(0.878 ns) + CELL(2.144 ns) = 3.022 ns; Loc. = PIN_E3; Fanout = 0; PIN Node = 'salida\[2\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.022 ns" { proximoestado.admision salida[2] } "NODE_NAME" } } { "motorcombustion.vhd" "" { Text "C:/Documents and Settings/Alejandro Aguilar/My Documents/UNIVALLE/Noveno semestre/Prototipado Rapido y VHDL/Tarea2 VHDL/motorcombustion/motorcombustion.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.144 ns ( 70.95 % ) " "Info: Total cell delay = 2.144 ns ( 70.95 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.878 ns ( 29.05 % ) " "Info: Total interconnect delay = 0.878 ns ( 29.05 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.022 ns" { proximoestado.admision salida[2] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.022 ns" { proximoestado.admision salida[2] } { 0.000ns 0.878ns } { 0.000ns 2.144ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.493 ns" { clock clock~clkctrl proximoestado.admision } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.493 ns" { clock clock~combout clock~clkctrl proximoestado.admision } { 0.000ns 0.000ns 0.343ns 0.678ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.022 ns" { proximoestado.admision salida[2] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.022 ns" { proximoestado.admision salida[2] } { 0.000ns 0.878ns } { 0.000ns 2.144ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "113 " "Info: Allocated 113 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon Nov 26 13:40:35 2007 " "Info: Processing ended: Mon Nov 26 13:40:35 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}