📄 motorcombustion.tan.rpt
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Classic Timing Analyzer report for motorcombustion
Mon Nov 26 13:40:35 2007
Quartus II Version 7.1 Build 156 04/30/2007 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. Clock Settings Summary
5. Clock Setup: 'clock'
6. tco
7. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+------------------------------------------------+-------------------------------+------------------------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+------------------------------------------------+-------------------------------+------------------------+------------+----------+--------------+
; Worst-case tco ; N/A ; None ; 5.609 ns ; proximoestado.admision ; salida[2] ; clock ; -- ; 0 ;
; Clock Setup: 'clock' ; N/A ; None ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; proximoestado.posicioninicial ; proximoestado.admision ; clock ; clock ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+------------------------------------------------+-------------------------------+------------------------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP2S15F484C3 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Default hold multicycle ; Same as Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clock ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clock' ;
+-------+------------------------------------------------+-------------------------------+-------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+-------------------------------+-------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; proximoestado.posicioninicial ; proximoestado.admision ; clock ; clock ; None ; None ; 0.560 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; proximoestado.retroceso ; proximoestado.escape ; clock ; clock ; None ; None ; 0.496 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; proximoestado.escape ; proximoestado.posicioninicial ; clock ; clock ; None ; None ; 0.423 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; proximoestado.admision ; proximoestado.compresion ; clock ; clock ; None ; None ; 0.421 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; proximoestado.explosion ; proximoestado.retroceso ; clock ; clock ; None ; None ; 0.419 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; proximoestado.compresion ; proximoestado.explosion ; clock ; clock ; None ; None ; 0.073 ns ;
+-------+------------------------------------------------+-------------------------------+-------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
+--------------------------------------------------------------------------------------+
; tco ;
+-------+--------------+------------+-------------------------+-----------+------------+
; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
+-------+--------------+------------+-------------------------+-----------+------------+
; N/A ; None ; 5.609 ns ; proximoestado.admision ; salida[2] ; clock ;
; N/A ; None ; 5.068 ns ; proximoestado.escape ; salida[1] ; clock ;
; N/A ; None ; 5.051 ns ; proximoestado.explosion ; salida[0] ; clock ;
+-------+--------------+------------+-------------------------+-----------+------------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
Info: Version 7.1 Build 156 04/30/2007 SJ Web Edition
Info: Processing started: Mon Nov 26 13:40:34 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off motorcombustion -c motorcombustion --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "clock" is an undefined clock
Info: Clock "clock" Internal fmax is restricted to 500.0 MHz between source register "proximoestado.posicioninicial" and destination register "proximoestado.admision"
Info: fmax restricted to clock pin edge rate 2.0 ns. Expand message to see actual delay path.
Info: + Longest register to register delay is 0.560 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X31_Y26_N3; Fanout = 1; REG Node = 'proximoestado.posicioninicial'
Info: 2: + IC(0.352 ns) + CELL(0.053 ns) = 0.405 ns; Loc. = LCCOMB_X31_Y26_N0; Fanout = 1; COMB Node = 'proximoestado.admision~8'
Info: 3: + IC(0.000 ns) + CELL(0.155 ns) = 0.560 ns; Loc. = LCFF_X31_Y26_N1; Fanout = 2; REG Node = 'proximoestado.admision'
Info: Total cell delay = 0.208 ns ( 37.14 % )
Info: Total interconnect delay = 0.352 ns ( 62.86 % )
Info: - Smallest clock skew is 0.000 ns
Info: + Shortest clock path from clock "clock" to destination register is 2.493 ns
Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clock'
Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 6; COMB Node = 'clock~clkctrl'
Info: 3: + IC(0.678 ns) + CELL(0.618 ns) = 2.493 ns; Loc. = LCFF_X31_Y26_N1; Fanout = 2; REG Node = 'proximoestado.admision'
Info: Total cell delay = 1.472 ns ( 59.05 % )
Info: Total interconnect delay = 1.021 ns ( 40.95 % )
Info: - Longest clock path from clock "clock" to source register is 2.493 ns
Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clock'
Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 6; COMB Node = 'clock~clkctrl'
Info: 3: + IC(0.678 ns) + CELL(0.618 ns) = 2.493 ns; Loc. = LCFF_X31_Y26_N3; Fanout = 1; REG Node = 'proximoestado.posicioninicial'
Info: Total cell delay = 1.472 ns ( 59.05 % )
Info: Total interconnect delay = 1.021 ns ( 40.95 % )
Info: + Micro clock to output delay of source is 0.094 ns
Info: + Micro setup delay of destination is 0.090 ns
Info: tco from clock "clock" to destination pin "salida[2]" through register "proximoestado.admision" is 5.609 ns
Info: + Longest clock path from clock "clock" to source register is 2.493 ns
Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clock'
Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 6; COMB Node = 'clock~clkctrl'
Info: 3: + IC(0.678 ns) + CELL(0.618 ns) = 2.493 ns; Loc. = LCFF_X31_Y26_N1; Fanout = 2; REG Node = 'proximoestado.admision'
Info: Total cell delay = 1.472 ns ( 59.05 % )
Info: Total interconnect delay = 1.021 ns ( 40.95 % )
Info: + Micro clock to output delay of source is 0.094 ns
Info: + Longest register to pin delay is 3.022 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X31_Y26_N1; Fanout = 2; REG Node = 'proximoestado.admision'
Info: 2: + IC(0.878 ns) + CELL(2.144 ns) = 3.022 ns; Loc. = PIN_E3; Fanout = 0; PIN Node = 'salida[2]'
Info: Total cell delay = 2.144 ns ( 70.95 % )
Info: Total interconnect delay = 0.878 ns ( 29.05 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
Info: Allocated 113 megabytes of memory during processing
Info: Processing ended: Mon Nov 26 13:40:35 2007
Info: Elapsed time: 00:00:01
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