prev_cmp_motor4tiempos.tan.qmsg

State Machine of Motor implemented in VHDL.

{ "Info" "ITDB_FULL_TPD_RESULT" "CLOCK Z\[0\] 8.086 ns Longest " "Info: Longest tpd from source pin \"CLOCK\" to destination pin \"Z\[0\]\" is 8.086 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns CLOCK 1 CLK PIN_N20 3 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 3; CLK Node = 'CLOCK'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK } "NODE_NAME" } } { "motor4tiempos.vhd" "" { Text "C:/Documents and Settings/Alejandro Aguilar/My Documents/My Quartus Documents/tarea2/motor4tiempos.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.085 ns) + CELL(0.272 ns) 5.211 ns Z~9 2 COMB LCCOMB_X14_Y7_N28 1 " "Info: 2: + IC(4.085 ns) + CELL(0.272 ns) = 5.211 ns; Loc. = LCCOMB_X14_Y7_N28; Fanout = 1; COMB Node = 'Z~9'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.357 ns" { CLOCK Z~9 } "NODE_NAME" } } { "motor4tiempos.vhd" "" { Text "C:/Documents and Settings/Alejandro Aguilar/My Documents/My Quartus Documents/tarea2/motor4tiempos.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.883 ns) + CELL(1.992 ns) 8.086 ns Z\[0\] 3 PIN PIN_AB16 0 " "Info: 3: + IC(0.883 ns) + CELL(1.992 ns) = 8.086 ns; Loc. = PIN_AB16; Fanout = 0; PIN Node = 'Z\[0\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.875 ns" { Z~9 Z[0] } "NODE_NAME" } } { "motor4tiempos.vhd" "" { Text "C:/Documents and Settings/Alejandro Aguilar/My Documents/My Quartus Documents/tarea2/motor4tiempos.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.118 ns ( 38.56 % ) " "Info: Total cell delay = 3.118 ns ( 38.56 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.968 ns ( 61.44 % ) " "Info: Total interconnect delay = 4.968 ns ( 61.44 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "8.086 ns" { CLOCK Z~9 Z[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "8.086 ns" { CLOCK CLOCK~combout Z~9 Z[0] } { 0.000ns 0.000ns 4.085ns 0.883ns } { 0.000ns 0.854ns 0.272ns 1.992ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 6 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "109 " "Info: Allocated 109 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Tue Oct 23 18:14:25 2007 " "Info: Processing ended: Tue Oct 23 18:14:25 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}