prev_cmp_motor4tiempos.tan.qmsg

State Machine of Motor implemented in VHDL.

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "PRESENT.s3 " "Info: Detected ripple clock \"PRESENT.s3\" as buffer" {  } { { "motor4tiempos.vhd" "" { Text "C:/Documents and Settings/Alejandro Aguilar/My Documents/My Quartus Documents/tarea2/motor4tiempos.vhd" 13 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "PRESENT.s3" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "CLOCK register register PRESENT.s3 PRESENT.s4 500.0 MHz Internal " "Info: Clock \"CLOCK\" Internal fmax is restricted to 500.0 MHz between source register \"PRESENT.s3\" and destination register \"PRESENT.s4\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.0 ns " "Info: fmax restricted to clock pin edge rate 2.0 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.530 ns + Longest register register " "Info: + Longest register to register delay is 0.530 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns PRESENT.s3 1 REG LCFF_X14_Y7_N29 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X14_Y7_N29; Fanout = 3; REG Node = 'PRESENT.s3'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { PRESENT.s3 } "NODE_NAME" } } { "motor4tiempos.vhd" "" { Text "C:/Documents and Settings/Alejandro Aguilar/My Documents/My Quartus Documents/tarea2/motor4tiempos.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.221 ns) + CELL(0.309 ns) 0.530 ns PRESENT.s4 2 REG LCFF_X14_Y7_N19 1 " "Info: 2: + IC(0.221 ns) + CELL(0.309 ns) = 0.530 ns; Loc. = LCFF_X14_Y7_N19; Fanout = 1; REG Node = 'PRESENT.s4'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.530 ns" { PRESENT.s3 PRESENT.s4 } "NODE_NAME" } } { "motor4tiempos.vhd" "" { Text "C:/Documents and Settings/Alejandro Aguilar/My Documents/My Quartus Documents/tarea2/motor4tiempos.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.309 ns ( 58.30 % ) " "Info: Total cell delay = 0.309 ns ( 58.30 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.221 ns ( 41.70 % ) " "Info: Total interconnect delay = 0.221 ns ( 41.70 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.530 ns" { PRESENT.s3 PRESENT.s4 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "0.530 ns" { PRESENT.s3 PRESENT.s4 } { 0.000ns 0.221ns } { 0.000ns 0.309ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.199 ns - Smallest " "Info: - Smallest clock skew is -0.199 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK destination 2.449 ns + Shortest register " "Info: + Shortest clock path from clock \"CLOCK\" to destination register is 2.449 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns CLOCK 1 CLK PIN_N20 3 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 3; CLK Node = 'CLOCK'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK } "NODE_NAME" } } { "motor4tiempos.vhd" "" { Text "C:/Documents and Settings/Alejandro Aguilar/My Documents/My Quartus Documents/tarea2/motor4tiempos.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns CLOCK~clkctrl 2 COMB CLKCTRL_G3 5 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 5; COMB Node = 'CLOCK~clkctrl'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { CLOCK CLOCK~clkctrl } "NODE_NAME" } } { "motor4tiempos.vhd" "" { Text "C:/Documents and Settings/Alejandro Aguilar/My Documents/My Quartus Documents/tarea2/motor4tiempos.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.634 ns) + CELL(0.618 ns) 2.449 ns PRESENT.s4 3 REG LCFF_X14_Y7_N19 1 " "Info: 3: + IC(0.634 ns) + CELL(0.618 ns) = 2.449 ns; Loc. = LCFF_X14_Y7_N19; Fanout = 1; REG Node = 'PRESENT.s4'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.252 ns" { CLOCK~clkctrl PRESENT.s4 } "NODE_NAME" } } { "motor4tiempos.vhd" "" { Text "C:/Documents and Settings/Alejandro Aguilar/My Documents/My Quartus Documents/tarea2/motor4tiempos.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 60.11 % ) " "Info: Total cell delay = 1.472 ns ( 60.11 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.977 ns ( 39.89 % ) " "Info: Total interconnect delay = 0.977 ns ( 39.89 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.449 ns" { CLOCK CLOCK~clkctrl PRESENT.s4 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.449 ns" { CLOCK CLOCK~combout CLOCK~clkctrl PRESENT.s4 } { 0.000ns 0.000ns 0.343ns 0.634ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK source 2.648 ns - Longest register " "Info: - Longest clock path from clock \"CLOCK\" to source register is 2.648 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns CLOCK 1 CLK PIN_N20 3 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 3; CLK Node = 'CLOCK'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK } "NODE_NAME" } } { "motor4tiempos.vhd" "" { Text "C:/Documents and Settings/Alejandro Aguilar/My Documents/My Quartus Documents/tarea2/motor4tiempos.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.176 ns) + CELL(0.618 ns) 2.648 ns PRESENT.s3 2 REG LCFF_X14_Y7_N29 3 " "Info: 2: + IC(1.176 ns) + CELL(0.618 ns) = 2.648 ns; Loc. = LCFF_X14_Y7_N29; Fanout = 3; REG Node = 'PRESENT.s3'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.794 ns" { CLOCK PRESENT.s3 } "NODE_NAME" } } { "motor4tiempos.vhd" "" { Text "C:/Documents and Settings/Alejandro Aguilar/My Documents/My Quartus Documents/tarea2/motor4tiempos.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 55.59 % ) " "Info: Total cell delay = 1.472 ns ( 55.59 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.176 ns ( 44.41 % ) " "Info: Total interconnect delay = 1.176 ns ( 44.41 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.648 ns" { CLOCK PRESENT.s3 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.648 ns" { CLOCK CLOCK~combout PRESENT.s3 } { 0.000ns 0.000ns 1.176ns } { 0.000ns 0.854ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.449 ns" { CLOCK CLOCK~clkctrl PRESENT.s4 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.449 ns" { CLOCK CLOCK~combout CLOCK~clkctrl PRESENT.s4 } { 0.000ns 0.000ns 0.343ns 0.634ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.648 ns" { CLOCK PRESENT.s3 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.648 ns" { CLOCK CLOCK~combout PRESENT.s3 } { 0.000ns 0.000ns 1.176ns } { 0.000ns 0.854ns 0.618ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.094 ns + " "Info: + Micro clock to output delay of source is 0.094 ns" {  } { { "motor4tiempos.vhd" "" { Text "C:/Documents and Settings/Alejandro Aguilar/My Documents/My Quartus Documents/tarea2/motor4tiempos.vhd" 13 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.090 ns + " "Info: + Micro setup delay of destination is 0.090 ns" {  } { { "motor4tiempos.vhd" "" { Text "C:/Documents and Settings/Alejandro Aguilar/My Documents/My Quartus Documents/tarea2/motor4tiempos.vhd" 13 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.530 ns" { PRESENT.s3 PRESENT.s4 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "0.530 ns" { PRESENT.s3 PRESENT.s4 } { 0.000ns 0.221ns } { 0.000ns 0.309ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.449 ns" { CLOCK CLOCK~clkctrl PRESENT.s4 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.449 ns" { CLOCK CLOCK~combout CLOCK~clkctrl PRESENT.s4 } { 0.000ns 0.000ns 0.343ns 0.634ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.648 ns" { CLOCK PRESENT.s3 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.648 ns" { CLOCK CLOCK~combout PRESENT.s3 } { 0.000ns 0.000ns 1.176ns } { 0.000ns 0.854ns 0.618ns } "" } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { PRESENT.s4 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { PRESENT.s4 } {  } {  } "" } } { "motor4tiempos.vhd" "" { Text "C:/Documents and Settings/Alejandro Aguilar/My Documents/My Quartus Documents/tarea2/motor4tiempos.vhd" 13 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "CLOCK 2 " "Warning: Circuit may not operate. Detected 2 non-operational path(s) clocked by clock \"CLOCK\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0 "" 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "PRESENT.s5 Z\[1\]\$latch CLOCK 2.737 ns " "Info: Found hold time violation between source  pin or register \"PRESENT.s5\" and destination pin or register \"Z\[1\]\$latch\" for clock \"CLOCK\" (Hold time is 2.737 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "3.072 ns + Largest " "Info: + Largest clock skew is 3.072 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK destination 5.521 ns + Longest register " "Info: + Longest clock path from clock \"CLOCK\" to destination register is 5.521 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns CLOCK 1 CLK PIN_N20 3 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 3; CLK Node = 'CLOCK'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK } "NODE_NAME" } } { "motor4tiempos.vhd" "" { Text "C:/Documents and Settings/Alejandro Aguilar/My Documents/My Quartus Documents/tarea2/motor4tiempos.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.176 ns) + CELL(0.712 ns) 2.742 ns PRESENT.s3 2 REG LCFF_X14_Y7_N29 3 " "Info: 2: + IC(1.176 ns) + CELL(0.712 ns) = 2.742 ns; Loc. = LCFF_X14_Y7_N29; Fanout = 3; REG Node = 'PRESENT.s3'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.888 ns" { CLOCK PRESENT.s3 } "NODE_NAME" } } { "motor4tiempos.vhd" "" { Text "C:/Documents and Settings/Alejandro Aguilar/My Documents/My Quartus Documents/tarea2/motor4tiempos.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.859 ns) + CELL(0.000 ns) 4.601 ns PRESENT.s3~clkctrl 3 COMB CLKCTRL_G5 2 " "Info: 3: + IC(1.859 ns) + CELL(0.000 ns) = 4.601 ns; Loc. = CLKCTRL_G5; Fanout = 2; COMB Node = 'PRESENT.s3~clkctrl'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.859 ns" { PRESENT.s3 PRESENT.s3~clkctrl } "NODE_NAME" } } { "motor4tiempos.vhd" "" { Text "C:/Documents and Settings/Alejandro Aguilar/My Documents/My Quartus Documents/tarea2/motor4tiempos.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.867 ns) + CELL(0.053 ns) 5.521 ns Z\[1\]\$latch 4 REG LCCOMB_X14_Y7_N16 1 " "Info: 4: + IC(0.867 ns) + CELL(0.053 ns) = 5.521 ns; Loc. = LCCOMB_X14_Y7_N16; Fanout = 1; REG Node = 'Z\[1\]\$latch'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.920 ns" { PRESENT.s3~clkctrl Z[1]$latch } "NODE_NAME" } } { "motor4tiempos.vhd" "" { Text "C:/Documents and Settings/Alejandro Aguilar/My Documents/My Quartus Documents/tarea2/motor4tiempos.vhd" 48 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.619 ns ( 29.32 % ) " "Info: Total cell delay = 1.619 ns ( 29.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.902 ns ( 70.68 % ) " "Info: Total interconnect delay = 3.902 ns ( 70.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.521 ns" { CLOCK PRESENT.s3 PRESENT.s3~clkctrl Z[1]$latch } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "5.521 ns" { CLOCK CLOCK~combout PRESENT.s3 PRESENT.s3~clkctrl Z[1]$latch } { 0.000ns 0.000ns 1.176ns 1.859ns 0.867ns } { 0.000ns 0.854ns 0.712ns 0.000ns 0.053ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK source 2.449 ns - Shortest register " "Info: - Shortest clock path from clock \"CLOCK\" to source register is 2.449 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns CLOCK 1 CLK PIN_N20 3 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 3; CLK Node = 'CLOCK'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK } "NODE_NAME" } } { "motor4tiempos.vhd" "" { Text "C:/Documents and Settings/Alejandro Aguilar/My Documents/My Quartus Documents/tarea2/motor4tiempos.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns CLOCK~clkctrl 2 COMB CLKCTRL_G3 5 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 5; COMB Node = 'CLOCK~clkctrl'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { CLOCK CLOCK~clkctrl } "NODE_NAME" } } { "motor4tiempos.vhd" "" { Text "C:/Documents and Settings/Alejandro Aguilar/My Documents/My Quartus Documents/tarea2/motor4tiempos.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.634 ns) + CELL(0.618 ns) 2.449 ns PRESENT.s5 3 REG LCFF_X14_Y7_N17 2 " "Info: 3: + IC(0.634 ns) + CELL(0.618 ns) = 2.449 ns; Loc. = LCFF_X14_Y7_N17; Fanout = 2; REG Node = 'PRESENT.s5'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.252 ns" { CLOCK~clkctrl PRESENT.s5 } "NODE_NAME" } } { "motor4tiempos.vhd" "" { Text "C:/Documents and Settings/Alejandro Aguilar/My Documents/My Quartus Documents/tarea2/motor4tiempos.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 60.11 % ) " "Info: Total cell delay = 1.472 ns ( 60.11 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.977 ns ( 39.89 % ) " "Info: Total interconnect delay = 0.977 ns ( 39.89 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.449 ns" { CLOCK CLOCK~clkctrl PRESENT.s5 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.449 ns" { CLOCK CLOCK~combout CLOCK~clkctrl PRESENT.s5 } { 0.000ns 0.000ns 0.343ns 0.634ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.521 ns" { CLOCK PRESENT.s3 PRESENT.s3~clkctrl Z[1]$latch } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "5.521 ns" { CLOCK CLOCK~combout PRESENT.s3 PRESENT.s3~clkctrl Z[1]$latch } { 0.000ns 0.000ns 1.176ns 1.859ns 0.867ns } { 0.000ns 0.854ns 0.712ns 0.000ns 0.053ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.449 ns" { CLOCK CLOCK~clkctrl PRESENT.s5 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.449 ns" { CLOCK CLOCK~combout CLOCK~clkctrl PRESENT.s5 } { 0.000ns 0.000ns 0.343ns 0.634ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.094 ns - " "Info: - Micro clock to output delay of source is 0.094 ns" {  } { { "motor4tiempos.vhd" "" { Text "C:/Documents and Settings/Alejandro Aguilar/My Documents/My Quartus Documents/tarea2/motor4tiempos.vhd" 13 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.241 ns - Shortest register register " "Info: - Shortest register to register delay is 0.241 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns PRESENT.s5 1 REG LCFF_X14_Y7_N17 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X14_Y7_N17; Fanout = 2; REG Node = 'PRESENT.s5'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { PRESENT.s5 } "NODE_NAME" } } { "motor4tiempos.vhd" "" { Text "C:/Documents and Settings/Alejandro Aguilar/My Documents/My Quartus Documents/tarea2/motor4tiempos.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.241 ns) 0.241 ns Z\[1\]\$latch 2 REG LCCOMB_X14_Y7_N16 1 " "Info: 2: + IC(0.000 ns) + CELL(0.241 ns) = 0.241 ns; Loc. = LCCOMB_X14_Y7_N16; Fanout = 1; REG Node = 'Z\[1\]\$latch'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.241 ns" { PRESENT.s5 Z[1]$latch } "NODE_NAME" } } { "motor4tiempos.vhd" "" { Text "C:/Documents and Settings/Alejandro Aguilar/My Documents/My Quartus Documents/tarea2/motor4tiempos.vhd" 48 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.241 ns ( 100.00 % ) " "Info: Total cell delay = 0.241 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.241 ns" { PRESENT.s5 Z[1]$latch } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "0.241 ns" { PRESENT.s5 Z[1]$latch } { 0.000ns 0.000ns } { 0.000ns 0.241ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.000 ns + " "Info: + Micro hold delay of destination is 0.000 ns" {  } { { "motor4tiempos.vhd" "" { Text "C:/Documents and Settings/Alejandro Aguilar/My Documents/My Quartus Documents/tarea2/motor4tiempos.vhd" 48 0 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.521 ns" { CLOCK PRESENT.s3 PRESENT.s3~clkctrl Z[1]$latch } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "5.521 ns" { CLOCK CLOCK~combout PRESENT.s3 PRESENT.s3~clkctrl Z[1]$latch } { 0.000ns 0.000ns 1.176ns 1.859ns 0.867ns } { 0.000ns 0.854ns 0.712ns 0.000ns 0.053ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.449 ns" { CLOCK CLOCK~clkctrl PRESENT.s5 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.449 ns" { CLOCK CLOCK~combout CLOCK~clkctrl PRESENT.s5 } { 0.000ns 0.000ns 0.343ns 0.634ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.241 ns" { PRESENT.s5 Z[1]$latch } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "0.241 ns" { PRESENT.s5 Z[1]$latch } { 0.000ns 0.000ns } { 0.000ns 0.241ns } "" } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLOCK Z\[2\] Z\[2\]\$latch 9.334 ns register " "Info: tco from clock \"CLOCK\" to destination pin \"Z\[2\]\" through register \"Z\[2\]\$latch\" is 9.334 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK source 5.519 ns + Longest register " "Info: + Longest clock path from clock \"CLOCK\" to source register is 5.519 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns CLOCK 1 CLK PIN_N20 3 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 3; CLK Node = 'CLOCK'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK } "NODE_NAME" } } { "motor4tiempos.vhd" "" { Text "C:/Documents and Settings/Alejandro Aguilar/My Documents/My Quartus Documents/tarea2/motor4tiempos.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.176 ns) + CELL(0.712 ns) 2.742 ns PRESENT.s3 2 REG LCFF_X14_Y7_N29 3 " "Info: 2: + IC(1.176 ns) + CELL(0.712 ns) = 2.742 ns; Loc. = LCFF_X14_Y7_N29; Fanout = 3; REG Node = 'PRESENT.s3'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.888 ns" { CLOCK PRESENT.s3 } "NODE_NAME" } } { "motor4tiempos.vhd" "" { Text "C:/Documents and Settings/Alejandro Aguilar/My Documents/My Quartus Documents/tarea2/motor4tiempos.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.859 ns) + CELL(0.000 ns) 4.601 ns PRESENT.s3~clkctrl 3 COMB CLKCTRL_G5 2 " "Info: 3: + IC(1.859 ns) + CELL(0.000 ns) = 4.601 ns; Loc. = CLKCTRL_G5; Fanout = 2; COMB Node = 'PRESENT.s3~clkctrl'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.859 ns" { PRESENT.s3 PRESENT.s3~clkctrl } "NODE_NAME" } } { "motor4tiempos.vhd" "" { Text "C:/Documents and Settings/Alejandro Aguilar/My Documents/My Quartus Documents/tarea2/motor4tiempos.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.865 ns) + CELL(0.053 ns) 5.519 ns Z\[2\]\$latch 4 REG LCCOMB_X14_Y7_N12 1 " "Info: 4: + IC(0.865 ns) + CELL(0.053 ns) = 5.519 ns; Loc. = LCCOMB_X14_Y7_N12; Fanout = 1; REG Node = 'Z\[2\]\$latch'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.918 ns" { PRESENT.s3~clkctrl Z[2]$latch } "NODE_NAME" } } { "motor4tiempos.vhd" "" { Text "C:/Documents and Settings/Alejandro Aguilar/My Documents/My Quartus Documents/tarea2/motor4tiempos.vhd" 48 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.619 ns ( 29.34 % ) " "Info: Total cell delay = 1.619 ns ( 29.34 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.900 ns ( 70.66 % ) " "Info: Total interconnect delay = 3.900 ns ( 70.66 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.519 ns" { CLOCK PRESENT.s3 PRESENT.s3~clkctrl Z[2]$latch } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "5.519 ns" { CLOCK CLOCK~combout PRESENT.s3 PRESENT.s3~clkctrl Z[2]$latch } { 0.000ns 0.000ns 1.176ns 1.859ns 0.865ns } { 0.000ns 0.854ns 0.712ns 0.000ns 0.053ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.000 ns + " "Info: + Micro clock to output delay of source is 0.000 ns" {  } { { "motor4tiempos.vhd" "" { Text "C:/Documents and Settings/Alejandro Aguilar/My Documents/My Quartus Documents/tarea2/motor4tiempos.vhd" 48 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.815 ns + Longest register pin " "Info: + Longest register to pin delay is 3.815 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Z\[2\]\$latch 1 REG LCCOMB_X14_Y7_N12 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCCOMB_X14_Y7_N12; Fanout = 1; REG Node = 'Z\[2\]\$latch'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { Z[2]$latch } "NODE_NAME" } } { "motor4tiempos.vhd" "" { Text "C:/Documents and Settings/Alejandro Aguilar/My Documents/My Quartus Documents/tarea2/motor4tiempos.vhd" 48 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.833 ns) + CELL(1.982 ns) 3.815 ns Z\[2\] 2 PIN PIN_A15 0 " "Info: 2: + IC(1.833 ns) + CELL(1.982 ns) = 3.815 ns; Loc. = PIN_A15; Fanout = 0; PIN Node = 'Z\[2\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.815 ns" { Z[2]$latch Z[2] } "NODE_NAME" } } { "motor4tiempos.vhd" "" { Text "C:/Documents and Settings/Alejandro Aguilar/My Documents/My Quartus Documents/tarea2/motor4tiempos.vhd" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.982 ns ( 51.95 % ) " "Info: Total cell delay = 1.982 ns ( 51.95 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.833 ns ( 48.05 % ) " "Info: Total interconnect delay = 1.833 ns ( 48.05 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.815 ns" { Z[2]$latch Z[2] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.815 ns" { Z[2]$latch Z[2] } { 0.000ns 1.833ns } { 0.000ns 1.982ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.519 ns" { CLOCK PRESENT.s3 PRESENT.s3~clkctrl Z[2]$latch } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "5.519 ns" { CLOCK CLOCK~combout PRESENT.s3 PRESENT.s3~clkctrl Z[2]$latch } { 0.000ns 0.000ns 1.176ns 1.859ns 0.865ns } { 0.000ns 0.854ns 0.712ns 0.000ns 0.053ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.815 ns" { Z[2]$latch Z[2] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.815 ns" { Z[2]$latch Z[2] } { 0.000ns 1.833ns } { 0.000ns 1.982ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}