motor4tiempos.vhd

State Machine of Motor implemented in VHDL.

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;

entity MOTOR4TIEMPOS is
port (CLOCK: in std_logic; Z: buffer std_logic_vector(2 downto 0));
end MOTOR4TIEMPOS;

architecture FSM_MOORE of MOTOR4TIEMPOS is
	type STATE is (S0, S1, S2, S3,S4,S5);
	signal PRESENT: STATE;
begin

process (CLOCK)
	begin
	
	if (CLOCK = '1' and CLOCK'EVENT) then
		
			case PRESENT is
		
			when S0 =>
				PRESENT <= S1;
			when S1 =>
				PRESENT <= S2;
			when S2 =>
				PRESENT <= S3;
			when S3 =>
				PRESENT <= S4;	
			when S4 =>
				PRESENT <= S5;
			when S5 =>
				PRESENT <= S0;
		
			end case;
			
	end if;

	
	
end process;

--Z2=VALVULA DE GASOLINA
--Z1=VALVULA DE ESCAPE
--Z0=CONTROL DE DISPARO DE LA BUJIA

process (PRESENT,CLOCK)
	begin
	case PRESENT is
	
	when S0 => 
		Z<="000";
		
	when S1 => 
		Z<="100";
		
	when S2 => 
		Z<="000";
		
	when S3 =>
		if CLOCK = '1' then
			Z(0)<='1';
		else
			Z(0)<='0';
		end if;
			
	when S4 => 
		Z<="000";
			
	when S5 => 
		Z<="010";
		
	end case;


end process;

end FSM_MOORE;