motor4tiempos.map.summary

State Machine of Motor implemented in VHDL.

Analysis & Synthesis Status : Successful - Tue Oct 23 18:13:44 2007
Quartus II Version : 7.1 Build 156 04/30/2007 SJ Web Edition
Revision Name : motor4tiempos
Top-level Entity Name : MOTOR4TIEMPOS
Family : Stratix II
Logic utilization : N/A
    Combinational ALUTs : 5
    Dedicated logic registers : 6
Total registers : 6
Total pins : 4
Total virtual pins : 0
Total block memory bits : 0
DSP block 9-bit elements : 0
Total PLLs : 0
Total DLLs : 0