motor4tiempos.map.rpt

State Machine of Motor implemented in VHDL.

+-------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary           ;
+-----------------------------------------------+-------+
; Resource                                      ; Usage ;
+-----------------------------------------------+-------+
; Estimated ALUTs Used                          ; 5     ;
; Dedicated logic registers                     ; 6     ;
;                                               ;       ;
; Estimated ALUTs Unavailable                   ; 0     ;
;                                               ;       ;
; Total combinational functions                 ; 5     ;
; Combinational ALUT usage by number of inputs  ;       ;
;     -- 7 input functions                      ; 0     ;
;     -- 6 input functions                      ; 0     ;
;     -- 5 input functions                      ; 0     ;
;     -- 4 input functions                      ; 0     ;
;     -- <=3 input functions                    ; 5     ;
;                                               ;       ;
; Combinational ALUTs by mode                   ;       ;
;     -- normal mode                            ; 5     ;
;     -- extended LUT mode                      ; 0     ;
;     -- arithmetic mode                        ; 0     ;
;     -- shared arithmetic mode                 ; 0     ;
;                                               ;       ;
; Estimated ALUT/register pairs used            ; 6     ;
;                                               ;       ;
; Total registers                               ; 6     ;
;     -- Dedicated logic registers              ; 6     ;
;     -- I/O registers                          ; 0     ;
;                                               ;       ;
; Estimated ALMs:  partially or completely used ; 3     ;
;                                               ;       ;
; I/O pins                                      ; 4     ;
; Maximum fan-out node                          ; CLOCK ;
; Maximum fan-out                               ; 7     ;
; Total fan-out                                 ; 25    ;
; Average fan-out                               ; 1.67  ;
+-----------------------------------------------+-------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                           ;
+----------------------------+-------------------+--------------+-------------------+--------------+---------+-----------+-----------+------+--------------+---------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Block Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------------+--------------+-------------------+--------------+---------+-----------+-----------+------+--------------+---------------------+--------------+
; |MOTOR4TIEMPOS             ; 5 (5)             ; 6 (6)        ; 0                 ; 0            ; 0       ; 0         ; 0         ; 4    ; 0            ; |MOTOR4TIEMPOS      ; work         ;
+----------------------------+-------------------+--------------+-------------------+--------------+---------+-----------+-----------+------+--------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


Encoding Type:  One-Hot
+------------------------------------------------------------------------------------------+
; State Machine - |MOTOR4TIEMPOS|PRESENT                                                   ;
+------------+------------+------------+------------+------------+------------+------------+
; Name       ; PRESENT.s5 ; PRESENT.s4 ; PRESENT.s3 ; PRESENT.s2 ; PRESENT.s1 ; PRESENT.s0 ;
+------------+------------+------------+------------+------------+------------+------------+
; PRESENT.s0 ; 0          ; 0          ; 0          ; 0          ; 0          ; 0          ;
; PRESENT.s1 ; 0          ; 0          ; 0          ; 0          ; 1          ; 1          ;
; PRESENT.s2 ; 0          ; 0          ; 0          ; 1          ; 0          ; 1          ;
; PRESENT.s3 ; 0          ; 0          ; 1          ; 0          ; 0          ; 1          ;
; PRESENT.s4 ; 0          ; 1          ; 0          ; 0          ; 0          ; 1          ;
; PRESENT.s5 ; 1          ; 0          ; 0          ; 0          ; 0          ; 1          ;
+------------+------------+------------+------------+------------+------------+------------+


+---------------------------------------------------------------------------------------------------+
; User-Specified and Inferred Latches                                                               ;
+----------------------------------------------------+---------------------+------------------------+
; Latch Name                                         ; Latch Enable Signal ; Free of Timing Hazards ;
+----------------------------------------------------+---------------------+------------------------+
; Z[1]$latch                                         ; PRESENT.s3          ; yes                    ;
; Z[2]$latch                                         ; PRESENT.s3          ; yes                    ;
; Number of user-specified and inferred latches = 2  ;                     ;                        ;
+----------------------------------------------------+---------------------+------------------------+
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 6     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.1 Build 156 04/30/2007 SJ Web Edition
    Info: Processing started: Tue Oct 23 18:13:36 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off motor4tiempos -c motor4tiempos
Info: Found 2 design units, including 1 entities, in source file motor4tiempos.vhd
    Info: Found design unit 1: MOTOR4TIEMPOS-FSM_MOORE
    Info: Found entity 1: MOTOR4TIEMPOS
Info: Elaborating entity "motor4tiempos" for the top level hierarchy
Warning (10631): VHDL Process Statement warning at motor4tiempos.vhd(48): inferring latch(es) for signal or variable "Z", which holds its previous value in one or more paths through the process
Info (10041): Inferred latch for "Z[1]" at motor4tiempos.vhd(48)
Info (10041): Inferred latch for "Z[2]" at motor4tiempos.vhd(48)
Info: State machine "|MOTOR4TIEMPOS|PRESENT" contains 6 states
Info: Selected Auto state machine encoding method for state machine "|MOTOR4TIEMPOS|PRESENT"
Info: Encoding result for state machine "|MOTOR4TIEMPOS|PRESENT"
    Info: Completed encoding using 6 state bits
        Info: Encoded state bit "PRESENT.s5"
        Info: Encoded state bit "PRESENT.s4"
        Info: Encoded state bit "PRESENT.s3"
        Info: Encoded state bit "PRESENT.s2"
        Info: Encoded state bit "PRESENT.s1"
        Info: Encoded state bit "PRESENT.s0"
    Info: State "|MOTOR4TIEMPOS|PRESENT.s0" uses code string "000000"
    Info: State "|MOTOR4TIEMPOS|PRESENT.s1" uses code string "000011"
    Info: State "|MOTOR4TIEMPOS|PRESENT.s2" uses code string "000101"
    Info: State "|MOTOR4TIEMPOS|PRESENT.s3" uses code string "001001"
    Info: State "|MOTOR4TIEMPOS|PRESENT.s4" uses code string "010001"
    Info: State "|MOTOR4TIEMPOS|PRESENT.s5" uses code string "100001"
Info: Implemented 13 device resources after synthesis - the final resource count might be different
    Info: Implemented 1 input pins
    Info: Implemented 3 output pins
    Info: Implemented 9 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning
    Info: Allocated 146 megabytes of memory during processing
    Info: Processing ended: Tue Oct 23 18:13:44 2007
    Info: Elapsed time: 00:00:08