motor4tiempos.fit.rpt

State Machine of Motor implemented in VHDL.

; Perform Physical Synthesis for Combinational Logic for Fitting        ; Off                            ; Off                            ;
; Perform Physical Synthesis for Combinational Logic for Performance    ; Off                            ; Off                            ;
; Perform Register Duplication for Performance                          ; Off                            ; Off                            ;
; Perform Logic to Memory Mapping for Fitting                           ; Off                            ; Off                            ;
; Perform Register Retiming for Performance                             ; Off                            ; Off                            ;
; Perform Asynchronous Signal Pipelining                                ; Off                            ; Off                            ;
; Fitter Effort                                                         ; Auto Fit                       ; Auto Fit                       ;
; Physical Synthesis Effort Level                                       ; Normal                         ; Normal                         ;
; Logic Cell Insertion - Logic Duplication                              ; Auto                           ; Auto                           ;
; Auto Register Duplication                                             ; Auto                           ; Auto                           ;
; Auto Global Clock                                                     ; On                             ; On                             ;
; Auto Global Register Control Signals                                  ; On                             ; On                             ;
; Stop After Congestion Map Generation                                  ; Off                            ; Off                            ;
; Save Intermediate Fitting Results                                     ; Off                            ; Off                            ;
; Use smart compilation                                                 ; Off                            ; Off                            ;
+-----------------------------------------------------------------------+--------------------------------+--------------------------------+


+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in C:/Documents and Settings/Alejandro Aguilar/My Documents/My Quartus Documents/tarea2/motor4tiempos.pin.


+---------------------------------------------------------------------+
; Fitter Resource Usage Summary                                       ;
+----------------------------------------------+----------------------+
; Resource                                     ; Usage                ;
+----------------------------------------------+----------------------+
; ALUTs Used                                   ; 5 / 12,480 ( < 1 % ) ;
; Dedicated logic registers                    ; 6 / 12,480 ( < 1 % ) ;
;                                              ;                      ;
; ALUTs Unavailable                            ; 0                    ;
;     -- Due to unpartnered 7 input function   ; 0                    ;
;     -- Due to unpartnered 6 input function   ; 0                    ;
;                                              ;                      ;
; Combinational ALUT usage by number of inputs ;                      ;
;     -- 7 input functions                     ; 0                    ;
;     -- 6 input functions                     ; 0                    ;
;     -- 5 input functions                     ; 0                    ;
;     -- 4 input functions                     ; 0                    ;
;     -- <=3 input functions                   ; 5                    ;
;                                              ;                      ;
; Combinational ALUTs by mode                  ;                      ;
;     -- normal mode                           ; 5                    ;
;     -- extended LUT mode                     ; 0                    ;
;     -- arithmetic mode                       ; 0                    ;
;     -- shared arithmetic mode                ; 0                    ;
;                                              ;                      ;
; Logic utilization                            ; 7 / 12,480 ( < 1 % ) ;
;     -- ALUT/register pairs used              ; 7                    ;
;         -- Combinational with no register    ; 1                    ;
;         -- Register only                     ; 2                    ;
;         -- Combinational with a register     ; 4                    ;
;     -- ALUT/register pairs unavailable       ; 0                    ;
;                                              ;                      ;
; Total registers*                             ; 6 / 14,410 ( < 1 % ) ;
;     -- Dedicated logic registers             ; 6 / 12,480 ( < 1 % ) ;
;     -- I/O registers                         ; 0 / 1,930 ( 0 % )    ;
;                                              ;                      ;
; ALMs:  partially or completely used          ; 4 / 6,240 ( < 1 % )  ;
;                                              ;                      ;
; Total LABs:  partially or completely used    ; 1 / 780 ( < 1 % )    ;
;                                              ;                      ;
; User inserted logic elements                 ; 0                    ;
; Virtual pins                                 ; 0                    ;
; I/O pins                                     ; 4 / 343 ( 1 % )      ;
;     -- Clock pins                            ; 1 / 16 ( 6 % )       ;
; Global signals                               ; 2                    ;
; M512s                                        ; 0 / 104 ( 0 % )      ;
; M4Ks                                         ; 0 / 78 ( 0 % )       ;
; Total block memory bits                      ; 0 / 419,328 ( 0 % )  ;
; Total block memory implementation bits       ; 0 / 419,328 ( 0 % )  ;
; DSP block 9-bit elements                     ; 0 / 96 ( 0 % )       ;
; PLLs                                         ; 0 / 6 ( 0 % )        ;
; Global clocks                                ; 2 / 16 ( 13 % )      ;
; Regional clocks                              ; 0 / 32 ( 0 % )       ;
; SERDES transmitters                          ; 0 / 38 ( 0 % )       ;
; SERDES receivers                             ; 0 / 42 ( 0 % )       ;
; Average interconnect usage                   ; 0%                   ;
; Peak interconnect usage                      ; 0%                   ;
; Maximum fan-out node                         ; CLOCK~clkctrl        ;
; Maximum fan-out                              ; 5                    ;
; Highest non-global fan-out signal            ; PRESENT.s3           ;
; Highest non-global fan-out                   ; 2                    ;
; Total fan-out                                ; 27                   ;
; Average fan-out                              ; 1.50                 ;
+----------------------------------------------+----------------------+
*  Register count does not include registers inside block RAM or DSP blocks.



+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Input Pins                                                                                                                                                                                                                                                  ;
+-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; Name  ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ;
+-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; CLOCK ; N20   ; 1        ; 0            ; 10           ; 1           ; 3                     ; 0                  ; yes    ; no             ; no            ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; Fitter               ;
+-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Output Pins                                                                                                                                                                                                                                                                           ;
+------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Output Enable Register ; Power Up High ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Location assigned by ; Load ;
+------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+
; Z[0] ; AB16  ; 8        ; 14           ; 0            ; 2           ; no              ; no                     ; no            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 24mA             ; Off         ; Fitter               ; 0 pF ;