motor4tiempos.tan.rpt

State Machine of Motor implemented in VHDL.

+--------------------------------------------------------------------+
; tco                                                                ;
+-------+--------------+------------+------------+------+------------+
; Slack ; Required tco ; Actual tco ; From       ; To   ; From Clock ;
+-------+--------------+------------+------------+------+------------+
; N/A   ; None         ; 9.334 ns   ; Z[2]$latch ; Z[2] ; CLOCK      ;
; N/A   ; None         ; 8.384 ns   ; Z[1]$latch ; Z[1] ; CLOCK      ;
; N/A   ; None         ; 5.858 ns   ; PRESENT.s3 ; Z[0] ; CLOCK      ;
+-------+--------------+------------+------------+------+------------+


+------------------------------------------------------------+
; tpd                                                        ;
+-------+-------------------+-----------------+-------+------+
; Slack ; Required P2P Time ; Actual P2P Time ; From  ; To   ;
+-------+-------------------+-----------------+-------+------+
; N/A   ; None              ; 8.086 ns        ; CLOCK ; Z[0] ;
+-------+-------------------+-----------------+-------+------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.1 Build 156 04/30/2007 SJ Web Edition
    Info: Processing started: Tue Oct 23 18:14:25 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off motor4tiempos -c motor4tiempos --timing_analysis_only
Warning: Timing Analysis is analyzing one or more combinational loops as latches
    Warning: Node "Z[1]$latch" is a latch
    Warning: Node "Z[2]$latch" is a latch
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "CLOCK" is an undefined clock
Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "PRESENT.s3" as buffer
Info: Clock "CLOCK" Internal fmax is restricted to 500.0 MHz between source register "PRESENT.s3" and destination register "PRESENT.s4"
    Info: fmax restricted to clock pin edge rate 2.0 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 0.530 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X14_Y7_N29; Fanout = 3; REG Node = 'PRESENT.s3'
            Info: 2: + IC(0.221 ns) + CELL(0.309 ns) = 0.530 ns; Loc. = LCFF_X14_Y7_N19; Fanout = 1; REG Node = 'PRESENT.s4'
            Info: Total cell delay = 0.309 ns ( 58.30 % )
            Info: Total interconnect delay = 0.221 ns ( 41.70 % )
        Info: - Smallest clock skew is -0.199 ns
            Info: + Shortest clock path from clock "CLOCK" to destination register is 2.449 ns
                Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 3; CLK Node = 'CLOCK'
                Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 5; COMB Node = 'CLOCK~clkctrl'
                Info: 3: + IC(0.634 ns) + CELL(0.618 ns) = 2.449 ns; Loc. = LCFF_X14_Y7_N19; Fanout = 1; REG Node = 'PRESENT.s4'
                Info: Total cell delay = 1.472 ns ( 60.11 % )
                Info: Total interconnect delay = 0.977 ns ( 39.89 % )
            Info: - Longest clock path from clock "CLOCK" to source register is 2.648 ns
                Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 3; CLK Node = 'CLOCK'
                Info: 2: + IC(1.176 ns) + CELL(0.618 ns) = 2.648 ns; Loc. = LCFF_X14_Y7_N29; Fanout = 3; REG Node = 'PRESENT.s3'
                Info: Total cell delay = 1.472 ns ( 55.59 % )
                Info: Total interconnect delay = 1.176 ns ( 44.41 % )
        Info: + Micro clock to output delay of source is 0.094 ns
        Info: + Micro setup delay of destination is 0.090 ns
Warning: Circuit may not operate. Detected 2 non-operational path(s) clocked by clock "CLOCK" with clock skew larger than data delay. See Compilation Report for details.
Info: Found hold time violation between source  pin or register "PRESENT.s5" and destination pin or register "Z[1]$latch" for clock "CLOCK" (Hold time is 2.737 ns)
    Info: + Largest clock skew is 3.072 ns
        Info: + Longest clock path from clock "CLOCK" to destination register is 5.521 ns
            Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 3; CLK Node = 'CLOCK'
            Info: 2: + IC(1.176 ns) + CELL(0.712 ns) = 2.742 ns; Loc. = LCFF_X14_Y7_N29; Fanout = 3; REG Node = 'PRESENT.s3'
            Info: 3: + IC(1.859 ns) + CELL(0.000 ns) = 4.601 ns; Loc. = CLKCTRL_G5; Fanout = 2; COMB Node = 'PRESENT.s3~clkctrl'
            Info: 4: + IC(0.867 ns) + CELL(0.053 ns) = 5.521 ns; Loc. = LCCOMB_X14_Y7_N16; Fanout = 1; REG Node = 'Z[1]$latch'
            Info: Total cell delay = 1.619 ns ( 29.32 % )
            Info: Total interconnect delay = 3.902 ns ( 70.68 % )
        Info: - Shortest clock path from clock "CLOCK" to source register is 2.449 ns
            Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 3; CLK Node = 'CLOCK'
            Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 5; COMB Node = 'CLOCK~clkctrl'
            Info: 3: + IC(0.634 ns) + CELL(0.618 ns) = 2.449 ns; Loc. = LCFF_X14_Y7_N17; Fanout = 2; REG Node = 'PRESENT.s5'
            Info: Total cell delay = 1.472 ns ( 60.11 % )
            Info: Total interconnect delay = 0.977 ns ( 39.89 % )
    Info: - Micro clock to output delay of source is 0.094 ns
    Info: - Shortest register to register delay is 0.241 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X14_Y7_N17; Fanout = 2; REG Node = 'PRESENT.s5'
        Info: 2: + IC(0.000 ns) + CELL(0.241 ns) = 0.241 ns; Loc. = LCCOMB_X14_Y7_N16; Fanout = 1; REG Node = 'Z[1]$latch'
        Info: Total cell delay = 0.241 ns ( 100.00 % )
    Info: + Micro hold delay of destination is 0.000 ns
Info: tco from clock "CLOCK" to destination pin "Z[2]" through register "Z[2]$latch" is 9.334 ns
    Info: + Longest clock path from clock "CLOCK" to source register is 5.519 ns
        Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 3; CLK Node = 'CLOCK'
        Info: 2: + IC(1.176 ns) + CELL(0.712 ns) = 2.742 ns; Loc. = LCFF_X14_Y7_N29; Fanout = 3; REG Node = 'PRESENT.s3'
        Info: 3: + IC(1.859 ns) + CELL(0.000 ns) = 4.601 ns; Loc. = CLKCTRL_G5; Fanout = 2; COMB Node = 'PRESENT.s3~clkctrl'
        Info: 4: + IC(0.865 ns) + CELL(0.053 ns) = 5.519 ns; Loc. = LCCOMB_X14_Y7_N12; Fanout = 1; REG Node = 'Z[2]$latch'
        Info: Total cell delay = 1.619 ns ( 29.34 % )
        Info: Total interconnect delay = 3.900 ns ( 70.66 % )
    Info: + Micro clock to output delay of source is 0.000 ns
    Info: + Longest register to pin delay is 3.815 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCCOMB_X14_Y7_N12; Fanout = 1; REG Node = 'Z[2]$latch'
        Info: 2: + IC(1.833 ns) + CELL(1.982 ns) = 3.815 ns; Loc. = PIN_A15; Fanout = 0; PIN Node = 'Z[2]'
        Info: Total cell delay = 1.982 ns ( 51.95 % )
        Info: Total interconnect delay = 1.833 ns ( 48.05 % )
Info: Longest tpd from source pin "CLOCK" to destination pin "Z[0]" is 8.086 ns
    Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 3; CLK Node = 'CLOCK'
    Info: 2: + IC(4.085 ns) + CELL(0.272 ns) = 5.211 ns; Loc. = LCCOMB_X14_Y7_N28; Fanout = 1; COMB Node = 'Z~9'
    Info: 3: + IC(0.883 ns) + CELL(1.992 ns) = 8.086 ns; Loc. = PIN_AB16; Fanout = 0; PIN Node = 'Z[0]'
    Info: Total cell delay = 3.118 ns ( 38.56 % )
    Info: Total interconnect delay = 4.968 ns ( 61.44 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 6 warnings
    Info: Allocated 109 megabytes of memory during processing
    Info: Processing ended: Tue Oct 23 18:14:25 2007
    Info: Elapsed time: 00:00:00