counter.hier_info

Counter Module 8 using comportamental description in VHDL

|counter
Clock => Q[2].CLK
Clock => Q[1].CLK
Clock => Q[0].CLK
Reset => Q[2].ACLR
Reset => Q[1].ACLR
Reset => Q[0].ACLR
Enable => Q[2].ENA
Enable => Q[1].ENA
Enable => Q[0].ENA
Load => Q~2.OUTPUTSELECT
Load => Q~1.OUTPUTSELECT
Load => Q~0.OUTPUTSELECT
Data[0] => Q~2.DATAB
Data[1] => Q~1.DATAB
Data[2] => Q~0.DATAB
Count[0] <= Q[0].DB_MAX_OUTPUT_PORT_TYPE
Count[1] <= Q[1].DB_MAX_OUTPUT_PORT_TYPE
Count[2] <= Q[2].DB_MAX_OUTPUT_PORT_TYPE