counter.tan.qmsg

Counter Module 8 using comportamental description in VHDL

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "Clock register register Q\[0\] Q\[2\] 500.0 MHz Internal " "Info: Clock \"Clock\" Internal fmax is restricted to 500.0 MHz between source register \"Q\[0\]\" and destination register \"Q\[2\]\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.0 ns " "Info: fmax restricted to clock pin edge rate 2.0 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.682 ns + Longest register register " "Info: + Longest register to register delay is 0.682 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Q\[0\] 1 REG LCFF_X39_Y3_N21 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X39_Y3_N21; Fanout = 4; REG Node = 'Q\[0\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { Q[0] } "NODE_NAME" } } { "counter.vhd" "" { Text "C:/Documents and Settings/Alejandro Aguilar/My Documents/UNIVALLE/Noveno semestre/Prototipado Rapido y VHDL/aguilar/CONTADOR MODULO 8/COMPORTAMENTAL/counter.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.255 ns) + CELL(0.272 ns) 0.527 ns Q~131 2 COMB LCCOMB_X39_Y3_N16 1 " "Info: 2: + IC(0.255 ns) + CELL(0.272 ns) = 0.527 ns; Loc. = LCCOMB_X39_Y3_N16; Fanout = 1; COMB Node = 'Q~131'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.527 ns" { Q[0] Q~131 } "NODE_NAME" } } { "counter.vhd" "" { Text "C:/Documents and Settings/Alejandro Aguilar/My Documents/UNIVALLE/Noveno semestre/Prototipado Rapido y VHDL/aguilar/CONTADOR MODULO 8/COMPORTAMENTAL/counter.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.155 ns) 0.682 ns Q\[2\] 3 REG LCFF_X39_Y3_N17 2 " "Info: 3: + IC(0.000 ns) + CELL(0.155 ns) = 0.682 ns; Loc. = LCFF_X39_Y3_N17; Fanout = 2; REG Node = 'Q\[2\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.155 ns" { Q~131 Q[2] } "NODE_NAME" } } { "counter.vhd" "" { Text "C:/Documents and Settings/Alejandro Aguilar/My Documents/UNIVALLE/Noveno semestre/Prototipado Rapido y VHDL/aguilar/CONTADOR MODULO 8/COMPORTAMENTAL/counter.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.427 ns ( 62.61 % ) " "Info: Total cell delay = 0.427 ns ( 62.61 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.255 ns ( 37.39 % ) " "Info: Total interconnect delay = 0.255 ns ( 37.39 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.682 ns" { Q[0] Q~131 Q[2] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "0.682 ns" { Q[0] Q~131 Q[2] } { 0.000ns 0.255ns 0.000ns } { 0.000ns 0.272ns 0.155ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clock destination 2.498 ns + Shortest register " "Info: + Shortest clock path from clock \"Clock\" to destination register is 2.498 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns Clock 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'Clock'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { Clock } "NODE_NAME" } } { "counter.vhd" "" { Text "C:/Documents and Settings/Alejandro Aguilar/My Documents/UNIVALLE/Noveno semestre/Prototipado Rapido y VHDL/aguilar/CONTADOR MODULO 8/COMPORTAMENTAL/counter.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns Clock~clkctrl 2 COMB CLKCTRL_G3 3 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 3; COMB Node = 'Clock~clkctrl'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { Clock Clock~clkctrl } "NODE_NAME" } } { "counter.vhd" "" { Text "C:/Documents and Settings/Alejandro Aguilar/My Documents/UNIVALLE/Noveno semestre/Prototipado Rapido y VHDL/aguilar/CONTADOR MODULO 8/COMPORTAMENTAL/counter.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.683 ns) + CELL(0.618 ns) 2.498 ns Q\[2\] 3 REG LCFF_X39_Y3_N17 2 " "Info: 3: + IC(0.683 ns) + CELL(0.618 ns) = 2.498 ns; Loc. = LCFF_X39_Y3_N17; Fanout = 2; REG Node = 'Q\[2\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.301 ns" { Clock~clkctrl Q[2] } "NODE_NAME" } } { "counter.vhd" "" { Text "C:/Documents and Settings/Alejandro Aguilar/My Documents/UNIVALLE/Noveno semestre/Prototipado Rapido y VHDL/aguilar/CONTADOR MODULO 8/COMPORTAMENTAL/counter.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 58.93 % ) " "Info: Total cell delay = 1.472 ns ( 58.93 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.026 ns ( 41.07 % ) " "Info: Total interconnect delay = 1.026 ns ( 41.07 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.498 ns" { Clock Clock~clkctrl Q[2] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.498 ns" { Clock Clock~combout Clock~clkctrl Q[2] } { 0.000ns 0.000ns 0.343ns 0.683ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clock source 2.498 ns - Longest register " "Info: - Longest clock path from clock \"Clock\" to source register is 2.498 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns Clock 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'Clock'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { Clock } "NODE_NAME" } } { "counter.vhd" "" { Text "C:/Documents and Settings/Alejandro Aguilar/My Documents/UNIVALLE/Noveno semestre/Prototipado Rapido y VHDL/aguilar/CONTADOR MODULO 8/COMPORTAMENTAL/counter.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns Clock~clkctrl 2 COMB CLKCTRL_G3 3 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 3; COMB Node = 'Clock~clkctrl'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { Clock Clock~clkctrl } "NODE_NAME" } } { "counter.vhd" "" { Text "C:/Documents and Settings/Alejandro Aguilar/My Documents/UNIVALLE/Noveno semestre/Prototipado Rapido y VHDL/aguilar/CONTADOR MODULO 8/COMPORTAMENTAL/counter.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.683 ns) + CELL(0.618 ns) 2.498 ns Q\[0\] 3 REG LCFF_X39_Y3_N21 4 " "Info: 3: + IC(0.683 ns) + CELL(0.618 ns) = 2.498 ns; Loc. = LCFF_X39_Y3_N21; Fanout = 4; REG Node = 'Q\[0\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.301 ns" { Clock~clkctrl Q[0] } "NODE_NAME" } } { "counter.vhd" "" { Text "C:/Documents and Settings/Alejandro Aguilar/My Documents/UNIVALLE/Noveno semestre/Prototipado Rapido y VHDL/aguilar/CONTADOR MODULO 8/COMPORTAMENTAL/counter.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 58.93 % ) " "Info: Total cell delay = 1.472 ns ( 58.93 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.026 ns ( 41.07 % ) " "Info: Total interconnect delay = 1.026 ns ( 41.07 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.498 ns" { Clock Clock~clkctrl Q[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.498 ns" { Clock Clock~combout Clock~clkctrl Q[0] } { 0.000ns 0.000ns 0.343ns 0.683ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.498 ns" { Clock Clock~clkctrl Q[2] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.498 ns" { Clock Clock~combout Clock~clkctrl Q[2] } { 0.000ns 0.000ns 0.343ns 0.683ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.498 ns" { Clock Clock~clkctrl Q[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.498 ns" { Clock Clock~combout Clock~clkctrl Q[0] } { 0.000ns 0.000ns 0.343ns 0.683ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.094 ns + " "Info: + Micro clock to output delay of source is 0.094 ns" {  } { { "counter.vhd" "" { Text "C:/Documents and Settings/Alejandro Aguilar/My Documents/UNIVALLE/Noveno semestre/Prototipado Rapido y VHDL/aguilar/CONTADOR MODULO 8/COMPORTAMENTAL/counter.vhd" 21 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.090 ns + " "Info: + Micro setup delay of destination is 0.090 ns" {  } { { "counter.vhd" "" { Text "C:/Documents and Settings/Alejandro Aguilar/My Documents/UNIVALLE/Noveno semestre/Prototipado Rapido y VHDL/aguilar/CONTADOR MODULO 8/COMPORTAMENTAL/counter.vhd" 21 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.682 ns" { Q[0] Q~131 Q[2] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "0.682 ns" { Q[0] Q~131 Q[2] } { 0.000ns 0.255ns 0.000ns } { 0.000ns 0.272ns 0.155ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.498 ns" { Clock Clock~clkctrl Q[2] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.498 ns" { Clock Clock~combout Clock~clkctrl Q[2] } { 0.000ns 0.000ns 0.343ns 0.683ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.498 ns" { Clock Clock~clkctrl Q[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.498 ns" { Clock Clock~combout Clock~clkctrl Q[0] } { 0.000ns 0.000ns 0.343ns 0.683ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { Q[2] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { Q[2] } {  } {  } "" } } { "counter.vhd" "" { Text "C:/Documents and Settings/Alejandro Aguilar/My Documents/UNIVALLE/Noveno semestre/Prototipado Rapido y VHDL/aguilar/CONTADOR MODULO 8/COMPORTAMENTAL/counter.vhd" 21 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "Q\[0\] Enable Clock 2.568 ns register " "Info: tsu for register \"Q\[0\]\" (data pin = \"Enable\", clock pin = \"Clock\") is 2.568 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.976 ns + Longest pin register " "Info: + Longest pin to register delay is 4.976 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.780 ns) 0.780 ns Enable 1 PIN PIN_R8 3 " "Info: 1: + IC(0.000 ns) + CELL(0.780 ns) = 0.780 ns; Loc. = PIN_R8; Fanout = 3; PIN Node = 'Enable'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { Enable } "NODE_NAME" } } { "counter.vhd" "" { Text "C:/Documents and Settings/Alejandro Aguilar/My Documents/UNIVALLE/Noveno semestre/Prototipado Rapido y VHDL/aguilar/CONTADOR MODULO 8/COMPORTAMENTAL/counter.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.450 ns) + CELL(0.746 ns) 4.976 ns Q\[0\] 2 REG LCFF_X39_Y3_N21 4 " "Info: 2: + IC(3.450 ns) + CELL(0.746 ns) = 4.976 ns; Loc. = LCFF_X39_Y3_N21; Fanout = 4; REG Node = 'Q\[0\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.196 ns" { Enable Q[0] } "NODE_NAME" } } { "counter.vhd" "" { Text "C:/Documents and Settings/Alejandro Aguilar/My Documents/UNIVALLE/Noveno semestre/Prototipado Rapido y VHDL/aguilar/CONTADOR MODULO 8/COMPORTAMENTAL/counter.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.526 ns ( 30.67 % ) " "Info: Total cell delay = 1.526 ns ( 30.67 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.450 ns ( 69.33 % ) " "Info: Total interconnect delay = 3.450 ns ( 69.33 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.976 ns" { Enable Q[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.976 ns" { Enable Enable~combout Q[0] } { 0.000ns 0.000ns 3.450ns } { 0.000ns 0.780ns 0.746ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.090 ns + " "Info: + Micro setup delay of destination is 0.090 ns" {  } { { "counter.vhd" "" { Text "C:/Documents and Settings/Alejandro Aguilar/My Documents/UNIVALLE/Noveno semestre/Prototipado Rapido y VHDL/aguilar/CONTADOR MODULO 8/COMPORTAMENTAL/counter.vhd" 21 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clock destination 2.498 ns - Shortest register " "Info: - Shortest clock path from clock \"Clock\" to destination register is 2.498 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns Clock 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'Clock'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { Clock } "NODE_NAME" } } { "counter.vhd" "" { Text "C:/Documents and Settings/Alejandro Aguilar/My Documents/UNIVALLE/Noveno semestre/Prototipado Rapido y VHDL/aguilar/CONTADOR MODULO 8/COMPORTAMENTAL/counter.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns Clock~clkctrl 2 COMB CLKCTRL_G3 3 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 3; COMB Node = 'Clock~clkctrl'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { Clock Clock~clkctrl } "NODE_NAME" } } { "counter.vhd" "" { Text "C:/Documents and Settings/Alejandro Aguilar/My Documents/UNIVALLE/Noveno semestre/Prototipado Rapido y VHDL/aguilar/CONTADOR MODULO 8/COMPORTAMENTAL/counter.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.683 ns) + CELL(0.618 ns) 2.498 ns Q\[0\] 3 REG LCFF_X39_Y3_N21 4 " "Info: 3: + IC(0.683 ns) + CELL(0.618 ns) = 2.498 ns; Loc. = LCFF_X39_Y3_N21; Fanout = 4; REG Node = 'Q\[0\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.301 ns" { Clock~clkctrl Q[0] } "NODE_NAME" } } { "counter.vhd" "" { Text "C:/Documents and Settings/Alejandro Aguilar/My Documents/UNIVALLE/Noveno semestre/Prototipado Rapido y VHDL/aguilar/CONTADOR MODULO 8/COMPORTAMENTAL/counter.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 58.93 % ) " "Info: Total cell delay = 1.472 ns ( 58.93 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.026 ns ( 41.07 % ) " "Info: Total interconnect delay = 1.026 ns ( 41.07 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.498 ns" { Clock Clock~clkctrl Q[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.498 ns" { Clock Clock~combout Clock~clkctrl Q[0] } { 0.000ns 0.000ns 0.343ns 0.683ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.976 ns" { Enable Q[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.976 ns" { Enable Enable~combout Q[0] } { 0.000ns 0.000ns 3.450ns } { 0.000ns 0.780ns 0.746ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.498 ns" { Clock Clock~clkctrl Q[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.498 ns" { Clock Clock~combout Clock~clkctrl Q[0] } { 0.000ns 0.000ns 0.343ns 0.683ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "Clock Count\[1\] Q\[1\] 5.346 ns register " "Info: tco from clock \"Clock\" to destination pin \"Count\[1\]\" through register \"Q\[1\]\" is 5.346 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clock source 2.498 ns + Longest register " "Info: + Longest clock path from clock \"Clock\" to source register is 2.498 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns Clock 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'Clock'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { Clock } "NODE_NAME" } } { "counter.vhd" "" { Text "C:/Documents and Settings/Alejandro Aguilar/My Documents/UNIVALLE/Noveno semestre/Prototipado Rapido y VHDL/aguilar/CONTADOR MODULO 8/COMPORTAMENTAL/counter.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns Clock~clkctrl 2 COMB CLKCTRL_G3 3 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 3; COMB Node = 'Clock~clkctrl'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { Clock Clock~clkctrl } "NODE_NAME" } } { "counter.vhd" "" { Text "C:/Documents and Settings/Alejandro Aguilar/My Documents/UNIVALLE/Noveno semestre/Prototipado Rapido y VHDL/aguilar/CONTADOR MODULO 8/COMPORTAMENTAL/counter.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.683 ns) + CELL(0.618 ns) 2.498 ns Q\[1\] 3 REG LCFF_X39_Y3_N23 3 " "Info: 3: + IC(0.683 ns) + CELL(0.618 ns) = 2.498 ns; Loc. = LCFF_X39_Y3_N23; Fanout = 3; REG Node = 'Q\[1\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.301 ns" { Clock~clkctrl Q[1] } "NODE_NAME" } } { "counter.vhd" "" { Text "C:/Documents and Settings/Alejandro Aguilar/My Documents/UNIVALLE/Noveno semestre/Prototipado Rapido y VHDL/aguilar/CONTADOR MODULO 8/COMPORTAMENTAL/counter.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 58.93 % ) " "Info: Total cell delay = 1.472 ns ( 58.93 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.026 ns ( 41.07 % ) " "Info: Total interconnect delay = 1.026 ns ( 41.07 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.498 ns" { Clock Clock~clkctrl Q[1] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.498 ns" { Clock Clock~combout Clock~clkctrl Q[1] } { 0.000ns 0.000ns 0.343ns 0.683ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.094 ns + " "Info: + Micro clock to output delay of source is 0.094 ns" {  } { { "counter.vhd" "" { Text "C:/Documents and Settings/Alejandro Aguilar/My Documents/UNIVALLE/Noveno semestre/Prototipado Rapido y VHDL/aguilar/CONTADOR MODULO 8/COMPORTAMENTAL/counter.vhd" 21 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.754 ns + Longest register pin " "Info: + Longest register to pin delay is 2.754 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Q\[1\] 1 REG LCFF_X39_Y3_N23 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X39_Y3_N23; Fanout = 3; REG Node = 'Q\[1\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { Q[1] } "NODE_NAME" } } { "counter.vhd" "" { Text "C:/Documents and Settings/Alejandro Aguilar/My Documents/UNIVALLE/Noveno semestre/Prototipado Rapido y VHDL/aguilar/CONTADOR MODULO 8/COMPORTAMENTAL/counter.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.620 ns) + CELL(2.134 ns) 2.754 ns Count\[1\] 2 PIN PIN_T3 0 " "Info: 2: + IC(0.620 ns) + CELL(2.134 ns) = 2.754 ns; Loc. = PIN_T3; Fanout = 0; PIN Node = 'Count\[1\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.754 ns" { Q[1] Count[1] } "NODE_NAME" } } { "counter.vhd" "" { Text "C:/Documents and Settings/Alejandro Aguilar/My Documents/UNIVALLE/Noveno semestre/Prototipado Rapido y VHDL/aguilar/CONTADOR MODULO 8/COMPORTAMENTAL/counter.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.134 ns ( 77.49 % ) " "Info: Total cell delay = 2.134 ns ( 77.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.620 ns ( 22.51 % ) " "Info: Total interconnect delay = 0.620 ns ( 22.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.754 ns" { Q[1] Count[1] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.754 ns" { Q[1] Count[1] } { 0.000ns 0.620ns } { 0.000ns 2.134ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.498 ns" { Clock Clock~clkctrl Q[1] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.498 ns" { Clock Clock~combout Clock~clkctrl Q[1] } { 0.000ns 0.000ns 0.343ns 0.683ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.754 ns" { Q[1] Count[1] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.754 ns" { Q[1] Count[1] } { 0.000ns 0.620ns } { 0.000ns 2.134ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "Q\[0\] Data\[0\] Clock -2.071 ns register " "Info: th for register \"Q\[0\]\" (data pin = \"Data\[0\]\", clock pin = \"Clock\") is -2.071 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clock destination 2.498 ns + Longest register " "Info: + Longest clock path from clock \"Clock\" to destination register is 2.498 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns Clock 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'Clock'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { Clock } "NODE_NAME" } } { "counter.vhd" "" { Text "C:/Documents and Settings/Alejandro Aguilar/My Documents/UNIVALLE/Noveno semestre/Prototipado Rapido y VHDL/aguilar/CONTADOR MODULO 8/COMPORTAMENTAL/counter.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns Clock~clkctrl 2 COMB CLKCTRL_G3 3 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 3; COMB Node = 'Clock~clkctrl'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { Clock Clock~clkctrl } "NODE_NAME" } } { "counter.vhd" "" { Text "C:/Documents and Settings/Alejandro Aguilar/My Documents/UNIVALLE/Noveno semestre/Prototipado Rapido y VHDL/aguilar/CONTADOR MODULO 8/COMPORTAMENTAL/counter.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.683 ns) + CELL(0.618 ns) 2.498 ns Q\[0\] 3 REG LCFF_X39_Y3_N21 4 " "Info: 3: + IC(0.683 ns) + CELL(0.618 ns) = 2.498 ns; Loc. = LCFF_X39_Y3_N21; Fanout = 4; REG Node = 'Q\[0\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.301 ns" { Clock~clkctrl Q[0] } "NODE_NAME" } } { "counter.vhd" "" { Text "C:/Documents and Settings/Alejandro Aguilar/My Documents/UNIVALLE/Noveno semestre/Prototipado Rapido y VHDL/aguilar/CONTADOR MODULO 8/COMPORTAMENTAL/counter.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 58.93 % ) " "Info: Total cell delay = 1.472 ns ( 58.93 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.026 ns ( 41.07 % ) " "Info: Total interconnect delay = 1.026 ns ( 41.07 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.498 ns" { Clock Clock~clkctrl Q[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.498 ns" { Clock Clock~combout Clock~clkctrl Q[0] } { 0.000ns 0.000ns 0.343ns 0.683ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.149 ns + " "Info: + Micro hold delay of destination is 0.149 ns" {  } { { "counter.vhd" "" { Text "C:/Documents and Settings/Alejandro Aguilar/My Documents/UNIVALLE/Noveno semestre/Prototipado Rapido y VHDL/aguilar/CONTADOR MODULO 8/COMPORTAMENTAL/counter.vhd" 21 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.718 ns - Shortest pin register " "Info: - Shortest pin to register delay is 4.718 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.810 ns) 0.810 ns Data\[0\] 1 PIN PIN_U5 1 " "Info: 1: + IC(0.000 ns) + CELL(0.810 ns) = 0.810 ns; Loc. = PIN_U5; Fanout = 1; PIN Node = 'Data\[0\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { Data[0] } "NODE_NAME" } } { "counter.vhd" "" { Text "C:/Documents and Settings/Alejandro Aguilar/My Documents/UNIVALLE/Noveno semestre/Prototipado Rapido y VHDL/aguilar/CONTADOR MODULO 8/COMPORTAMENTAL/counter.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.700 ns) + CELL(0.053 ns) 4.563 ns Q~129 2 COMB LCCOMB_X39_Y3_N20 1 " "Info: 2: + IC(3.700 ns) + CELL(0.053 ns) = 4.563 ns; Loc. = LCCOMB_X39_Y3_N20; Fanout = 1; COMB Node = 'Q~129'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.753 ns" { Data[0] Q~129 } "NODE_NAME" } } { "counter.vhd" "" { Text "C:/Documents and Settings/Alejandro Aguilar/My Documents/UNIVALLE/Noveno semestre/Prototipado Rapido y VHDL/aguilar/CONTADOR MODULO 8/COMPORTAMENTAL/counter.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.155 ns) 4.718 ns Q\[0\] 3 REG LCFF_X39_Y3_N21 4 " "Info: 3: + IC(0.000 ns) + CELL(0.155 ns) = 4.718 ns; Loc. = LCFF_X39_Y3_N21; Fanout = 4; REG Node = 'Q\[0\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.155 ns" { Q~129 Q[0] } "NODE_NAME" } } { "counter.vhd" "" { Text "C:/Documents and Settings/Alejandro Aguilar/My Documents/UNIVALLE/Noveno semestre/Prototipado Rapido y VHDL/aguilar/CONTADOR MODULO 8/COMPORTAMENTAL/counter.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.018 ns ( 21.58 % ) " "Info: Total cell delay = 1.018 ns ( 21.58 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.700 ns ( 78.42 % ) " "Info: Total interconnect delay = 3.700 ns ( 78.42 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.718 ns" { Data[0] Q~129 Q[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.718 ns" { Data[0] Data[0]~combout Q~129 Q[0] } { 0.000ns 0.000ns 3.700ns 0.000ns } { 0.000ns 0.810ns 0.053ns 0.155ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.498 ns" { Clock Clock~clkctrl Q[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.498 ns" { Clock Clock~combout Clock~clkctrl Q[0] } { 0.000ns 0.000ns 0.343ns 0.683ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.718 ns" { Data[0] Q~129 Q[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.718 ns" { Data[0] Data[0]~combout Q~129 Q[0] } { 0.000ns 0.000ns 3.700ns 0.000ns } { 0.000ns 0.810ns 0.053ns 0.155ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}