cpu_behav.vhd

this file is cpu code in vhdl

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    18:37:47 05/17/1985 
-- Design Name: 
-- Module Name:    cpu_behav - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity cpu_behav is
    Port ( clk,reset,ext_int,counter_clk : in  STD_LOGIC;
			p0 :in std_logic_vector(7 downto 0);
			p1,adress_bus :out std_logic_vector(7 downto 0);
			 wr_ext_ram,en_ext_ram:out  STD_LOGIC;
			data_bus :out std_logic_vector(7 downto 0)
			);
end cpu_behav;

architecture Behavioral of cpu_behav is

signal ir,acc,di_ram,do_ram:std_logic_vector(7 downto 0);
signal pc,addr1:std_logic_vector(7 downto 0);
signal acc16_1,acc16_2:std_logic_vector(15 downto 0);
signal clk1,ct,ts,tf,c,z,en_ext_int,en_int_timer:std_logic;
signal x,y:std_logic_vector(1 downto 0);
--signal en_ram,we_ram:std_logic;
signal timer:std_logic_vector(15 downto 0);

type state_type is (start_s,fetch1_s, fetch2_s, decode_s,mov00,mov01,mov02,
mov10,mov11,mov20,mov21,mov22,mov30,mov31,mov40,mov41,mov42,mov50,mov51,
mov60,mov61,mov62,mov70,mov71,mov72,mov80,mov81,mov90,mov91,mova0,mova1,
movb0,movb1,add0,add1,add2,add3,sub0,sub1,sub2,sub3,div0,div1,div2
,div3,mul0,mul1,mul2,mul3,dec0,dec1,dec2,inc0,inc1,inc2,com0,com1,com2,
com3,movc0,movc1,movc2,movd0,movd1,movd2,movd3,nop,nop0,setbts,clrbts,setbct,clrbct,jbtf,jbtf0,jbc,jbc0,
jbz,jbz0,halt_s,setbenex,clrentimer,setentimer,check_int,check_int0,
check_int1,int_timer1,int_timer2,int_ext1,int_ext2,clrbenex,ret0,ret1,jmp);

signal curr,nxt: state_type;

type memory is array(0 to 255) of std_logic_vector(7 downto 0);
signal ram : memory;

begin

process(clk,reset)
begin
if reset='1' then 
curr<=start_s;
--pc<="00000";
--a<=X"00";
--ir<=X"00";
elsif (clk'event and clk='1') then
curr<=nxt;
end if;
end process;
------------------------------------------------
process(ct,clk)
begin
	if ct='1' then 
		clk1<=counter_clk;
		else 
		clk1<=clk;
	end if;
end process;

------------------------------------------------
timer_process:process(ts)
begin
	if ts='1' then 
		if(clk1'event and clk1='1') then
				timer<=timer+ X"0001";
				if timer=X"ffff" then
					tf<='1';
					timer<=X"0000";
				else 
					tf<='0';		
				end if;
		end if;
		addr1<=X"84";
	ram(conv_integer(addr1))<=timer(7 downto 0);
		addr1<=X"85";
	ram(conv_integer(addr1))<=timer(15 downto 8);
	end if;
end process;
-------------------------------------------------
x1:process(tf,ext_int)
begin
case tf is
	when '0' =>
	x<="00";
	when '1' =>
	x<="01";
	when others =>
	x<="00";
end case;
case ext_int is
	when '0' =>
	y<="00";
	when '1' =>
	y<="10";
	when others =>
	y<="00";
end case;

end process;
-------------------------------------------------
process(curr)
begin
case curr is
	when start_s=>
	pc<="00000000";
	acc<=X"00";
	ir<=X"00";
	nxt<=fetch1_s;

	when fetch1_s=>
	do_ram<=ram(conv_integer(pc));
	nxt<=fetch2_s;

	when fetch2_s=>
	ir<=do_ram;
	pc<=pc+1;
	nxt<=decode_s;

	when decode_s=>
		case ir is
						when "00000000"=>
			nxt<=mov00;
			
						when "00000001"=>
			nxt<= mov10;

						when "00000010"=>
			nxt<=	mov20;

						when "00000011"=>
			nxt<=mov30;

						when "00000100"=>
			nxt<=mov40;
						when "00000101"=>
			nxt<=mov50;
						when "00000110"=>
			nxt<=mov60;
						when "00000111"=>
			nxt<=mov70;
						when "00001000"=>
			nxt<=mov80;
						when "00001001"=>
			nxt<=mov90;
						when "00001010"=>
			nxt<=mova0;
						when "00001011"=>
			nxt<=movb0;
						when "00001100"=>
			nxt<=add0;
						when "00001101"=>
			nxt<=sub0;
						when "00001110"=>
			nxt<=div0;
						when "00001111"=>
			nxt<=mul0;			 			
						when "00010000"=>
			nxt<=dec0;
						when "00010001"=>
			nxt<=inc0;
						when "00010010"=>
			nxt<=com0;
						when "00010011"=>
			nxt<=nop0;
						when "00010100"=>
			nxt<=movc0;
						when "00010101"=>
			nxt<=movd0;
						when "00010110"=>
			nxt<=setbts;		
						when "00010111"=>
			nxt<=clrbts;
						when "00011000"=>
			nxt<=setbct;
						when "00011001"=>
			nxt<=clrbct;
						when "00011010"=>
			nxt<=jbtf;
						when "00011011"=>
			nxt<=jbc;
						when "00011100"=>
			nxt<=jbz;
						when "00011101"=>
			nxt<=halt_s;
						when "00011110"=>
			nxt<=setbenex;
						when "00011111"=>
			nxt<=clrbenex;
						when "00100000"=>
			nxt<=ret0;
						when "00100001"=>
			nxt<=setentimer;
							when "00100010"=>
			nxt<=clrentimer;		
							when "00100011"=>
			nxt<=jmp;			
			
			
						
						when others=>
			nxt<=halt_s;
		end case;
when mov00=>
do_ram<=ram(conv_integer(pc));
pc<=pc+"00000001";
nxt<=mov01;

when mov01=>
acc<=ram(conv_integer(do_ram));
nxt<=mov02;

when mov02=>
addr1<=X"80";
ram(conv_integer(addr1))<=acc;
nxt<=check_int;
-------------------------------------------------------
when mov10=>
acc<=ram(conv_integer(pc));
pc<=pc+"00000001";
nxt<=mov11;

when mov11=>
addr1<=X"80";
ram(conv_integer(addr1))<=acc;
nxt<=check_int;
-------------------------------------------------------
when mov20=>
do_ram<=ram(conv_integer(pc));
pc<=pc+"00000001";
nxt<=mov21;

when mov21=>
acc<=ram(conv_integer(do_ram));
nxt<=mov22;

when mov22=>
addr1<=X"81";
ram(conv_integer(addr1))<=acc;
nxt<=check_int;
-------------------------------------------------------
when mov30=>
acc<=ram(conv_integer(pc));
pc<=pc+"00000001";
nxt<=mov31;

when mov31=>
addr1<=X"81";
ram(conv_integer(addr1))<=acc;
nxt<=check_int;
-------------------------------------------------------
when mov40=>
do_ram<=ram(conv_integer(pc));
pc<=pc+"00000001";
nxt<=mov41;

when mov41=>
acc<=ram(conv_integer(do_ram));
nxt<=mov42;

when mov42=>
addr1<=X"86";
ram(conv_integer(addr1))<=acc;
nxt<=check_int;
-------------------------------------------------------
when mov50=>
acc<=ram(conv_integer(pc));
pc<=pc+"00000001";
nxt<=mov51;

when mov51=>
addr1<=X"85";
ram(conv_integer(addr1))<=acc;
nxt<=check_int;
-------------------------------------------------------
when mov60=>
addr1<=X"86";
do_ram<=ram(conv_integer(addr1));
pc<=pc+"00000001";
nxt<=mov61;

when mov61=>
adress_bus<=do_ram;
en_ext_ram<='1';
nxt<=mov62;

when mov62=>
addr1<=X"80";
ram(conv_integer(addr1))<=do_ram;
nxt<=check_int;
------------------------------------------------------
when mov70=>
addr1<=X"86";
adress_bus<=ram(conv_integer(addr1));
pc<=pc+"00000001";
nxt<=mov71;

when mov71=>
addr1<=X"80";
do_ram<=ram(conv_integer(addr1));
nxt<=mov72;

when mov72=>
wr_ext_ram<='1';
nxt<=check_int;
------------------------------------------------------
when mov80=>
addr1<=X"80";
acc<=ram(conv_integer(addr1));
nxt<=mov81;

when mov81=>
addr1<=X"81";
ram(conv_integer(addr1))<=acc;
nxt<=check_int;
------------------------------------------------------
when mov90=>
addr1<=X"81";
acc<=ram(conv_integer(addr1));
nxt<=mov91;

when mov91=>
addr1<=X"80";
ram(conv_integer(addr1))<=acc;
nxt<=check_int;
------------------------------------------------------
when mova0=>
acc<=ram(conv_integer(pc));
pc<=pc+"00000001";
nxt<=mova1;

when mova1=>
ram(conv_integer(acc))<=p0;
nxt<=check_int;

------------------------------------------------------
when movb0=>
acc<=ram(conv_integer(pc));
pc<=pc+"00000001";
nxt<=movb1;

when movb1=>
p1<=ram(conv_integer(acc));
nxt<=check_int;
-----------------------------------------------------
when add0=>
addr1<=X"80";
acc<=ram(conv_integer(addr1));
acc16_1<=X"00" & acc;
nxt<=add1;

when add1=>
addr1<=X"81";
acc16_2<=X"00" & ram(conv_integer(addr1));
nxt<=add2;

when add2=>
acc16_1<=acc16_1+acc16_2;
nxt<=add3;

when add3=>
addr1<=X"80";
ram(conv_integer(addr1))<=acc16_1(7 downto 0);
c<=acc16_1(8);
if acc16_1(7 downto 0)="00000000" then
z<='1';
end if;
nxt<=check_int;



-----------------------------------------------------
when sub0=>
addr1<=X"80";
acc<=ram(conv_integer(addr1));
acc16_1<=X"00" & acc;
nxt<=sub1;

when sub1=>
addr1<=X"81";
acc16_2<=X"00" & ram(conv_integer(addr1));
nxt<=sub2;

when sub2=>
acc16_1<=acc16_1 - acc16_2;
nxt<=sub3;

when sub3=>
addr1<=X"80";
ram(conv_integer(addr1))<=acc16_1(7 downto 0);
c<=acc16_1(8);
if acc16_1(7 downto 0)="00000000" then
z<='1';
end if;
nxt<=check_int;
----------------------------------------------------
when mul0=>
addr1<=X"80";
acc<=ram(conv_integer(addr1));
acc16_1<=X"00" & acc;
nxt<=mul1;

when mul1=>
addr1<=X"81";
acc16_2<=X"00" & ram(conv_integer(addr1));
nxt<=mul2;

when mul2=>
acc16_1<=acc16_1 * acc16_2;
nxt<=mul3;

when mul3=>
addr1<=X"80";
ram(conv_integer(addr1))<=acc16_1(7 downto 0);
addr1<=X"81";
ram(conv_integer(addr1))<=acc16_1(15 downto 8);
nxt<=check_int;
----------------------------------------------------

when com0=>
addr1<=X"80";
acc<=ram(conv_integer(addr1));
acc16_1<=X"00" & acc;
nxt<=com1;

when com1=>
addr1<=X"81";
acc16_2<=X"00" & ram(conv_integer(addr1));
nxt<=com2;

when com2=>
acc16_1<=acc16_1 - acc16_2;
nxt<=com3;

when com3=>
c<=acc16_1(8);
if acc16_1(7 downto 0)="00000000" then
z<='1';
end if;
nxt<=check_int;
-----------------------------------------------------
when inc0=>
addr1<=X"80";
acc<=ram(conv_integer(addr1));
nxt<=inc1;

when inc1=>
acc<=acc + "00000001";
nxt<=inc2;

when inc2=>
addr1<=X"80";
ram(conv_integer(addr1))<=acc;
if acc="00000000" then
z<='1';
end if;
nxt<=check_int;
----------------------------------------------------
when dec0=>
addr1<=X"80";
acc<=ram(conv_integer(addr1));
nxt<=dec1;

when dec1=>
acc<=acc + "00000001";
nxt<=dec2;

when dec2=>
addr1<=X"80";
ram(conv_integer(addr1))<=acc;
if acc="00000000" then
z<='1';
end if;
nxt<=check_int;
----------------------------------------------------
when div0=>
addr1<=X"80";
acc<=ram(conv_integer(addr1));
acc16_1<=X"00" & acc;
nxt<=div1;

when div1=>
addr1<=X"81";
acc16_2<=X"00" & ram(conv_integer(addr1));
nxt<=div2;

when div2=>
acc16_1<=(acc16_1)/(acc16_2);
nxt<=div3;

when div3=>
addr1<=X"81";

ram(conv_integer(addr1))<=acc16_1(7 downto 0);
nxt<=check_int;
-----------------------------------------------------
when setbts=>
ts<='1';
nxt<=check_int;
-----------------------------------------------------
when clrbts=>
ts<='0';
nxt<=check_int;
-----------------------------------------------------
when setbct=>
ct<='1';
nxt<=check_int;
-----------------------------------------------------
when clrbct=>
ct<='0';
nxt<=check_int;
-----------------------------------------------------
when jbtf=>
		if tf='1' then
				do_ram<=ram(conv_integer(pc));
				nxt<=jbtf0;
				
				else
				nxt<=fetch1_s;
				end if;

when jbtf0=>
pc<=do_ram;
nxt<=check_int;
-----------------------------------------------------
when jbc=>
		if c='1' then
				do_ram<=ram(conv_integer(pc));
				nxt<=jbc0;
				
				else
				nxt<=fetch1_s;
				end if;

when jbc0=>
pc<=do_ram;
nxt<=check_int;
-----------------------------------------------------
when jbz=>
		if c='1' then
				do_ram<=ram(conv_integer(pc));
				nxt<=jbz0;
				
				else
				nxt<=fetch1_s;
				end if;

when jbz0=>
pc<=do_ram;
nxt<=check_int;
-----------------------------------------------------
when nop=>
nxt<=nop0;

when nop0=>
nxt<=check_int;

-----------------------------------------------------
when halt_s=>
nxt<=halt_s;
-----------------------------------------------------
when setbenex=>
en_ext_int<='1';
nxt<=check_int;
-----------------------------------------------------
when clrbenex=>
en_ext_int<='0';
nxt<=check_int;
-----------------------------------------------------
when setentimer=>
en_int_timer<='1';
nxt<=check_int;
-----------------------------------------------------
when clrentimer=>
en_int_timer<='0';
nxt<=check_int;
-----------------------------------------------------
when ret0=>
addr1<=X"90";
do_ram<=ram(conv_integer(addr1));
nxt<=ret1;

when ret1=>
pc<=do_ram;
nxt<=check_int;
-----------------------------------------------------
when jmp=>
do_ram<=ram(conv_integer(pc));
pc<=pc+"00000001";
nxt<=fetch1_s;
-----------------------------------------------------
when check_int=>
		case x is
		when "01" =>
		nxt<=check_int0;
		when "00" =>
		nxt<=fetch1_s;
		when others =>
		nxt<=fetch1_s;
		end case;
		
		case y is
		when "10" =>
		nxt<=check_int1;
		when "00" =>
		nxt<=fetch1_s;
		when others =>
		nxt<=fetch1_s;
		end case;
	
		
		
when check_int0=>
		case en_int_timer is
		when '1' =>		
		nxt<=int_timer1;
		when '0' =>		
		nxt<=fetch1_s;
		when others =>		
		nxt<=fetch1_s;
	end case;	



when check_int1=>
		case en_ext_int is
		when '1' =>	
		nxt<=int_ext1;
		when '0' =>	
		nxt<=fetch1_s;
		when others =>		
		nxt<=fetch1_s;
	end case;
----------------------------------------------
when int_ext1=>
addr1<=X"90";
ram(conv_integer(addr1))<=pc;
x<="00";
nxt<=int_ext2;

when int_ext2=>
pc<=X"03";
nxt<=fetch1_s;


------------------------------------------------
when int_timer1=>
addr1<=X"90";
ram(conv_integer(addr1))<=pc;
x<="00";
nxt<=int_timer2;

when int_timer2=>
pc<=X"0b";
nxt<=fetch1_s;
------------------------------------------------
when movc0=>
ts<='0';
nxt<=movc1;
------------------------------------------------
when movc1=>
timer(7 downto 0)<=ram(conv_integer(pc));
pc<=pc+X"01";
nxt<=movc2;
------------------------------------------------
when movc2=>
timer(15 downto 8)<=ram(conv_integer(pc));
nxt<=check_int;
-------------------------------------------------
when movd0=>
ts<='0';
nxt<=movd1;
-------------------------------------------------
when movd1=>
addr1<=ram(conv_integer(pc));
pc<=pc+X"01";
nxt<=movd2;
-------------------------------------------------
when movd2=>
timer(7 downto 0)<=ram(conv_integer(addr1));
addr1<=addr1+X"01";
nxt<=movd3;
-------------------------------------------------
when movd3=>
timer(15 downto 8)<=ram(conv_integer(addr1));
nxt<=check_int;

-------------------------------------------------
end case;
end process;

end;