keywords.lst

来自「主要用于大规模的测试生成方法」· LST 代码 · 共 336 行

ANGLE
BEHAVIOR
CALCULATED
CAPACITANCE
CENTERCENTER
CENTERLEFT
CENTERRIGHT
CHARGE
CONDUCTANCE
CURRENT
DISTANCE
DOCUMENT
ENERGY
EXTEND
FLUX
FREQUENCY
GENERIC
GRAPHIC
INDUCTANCE
INOUT
INPUT
LOGICMODEL
LOWERCENTER
LOWERLEFT
LOWERRIGHT
MASKLAYOUT
MASS
MEASURED
MX
MXR90
MY
MYR90
NETLIST
OUTPUT
PCBLAYOUT
POWER
R0
R180
R270
R90
REQUIRED
RESISTANCE
RIPPER
ROUND
SCHEMATIC
STRANGER
SYMBOLIC
TEMPERATURE
TIE
TIME
TRUNCATE
UPPERCENTER
UPPERLEFT
UPPERRIGHT
VOLTAGE
abs
acLoad
actual
after
and
annotate
apply
arc
array
arrayMacro
arrayRelatedInfo
arraySite
assign
atLeast
atMost
author
baseArray
becomes
between
block
boolean
booleanDisplay
booleanMap
borderPattern
borderWidth
boundingBox
build
ceiling
cell
cellRef
cellType
change
circle
collector
color
comment
commentGraphics
compound
concat
connectLocation
constant
constraint
contents
cornerType
criticality
currentMap
curve
cycle
dataOrigin
dcFaninLoad
dcFanoutLoad
dcMaxFanin
dcMaxFanout
delay
delta
derivation
design
designator
difference
direction
display
divide
dominates
dot
duration
e
edif
edifLevel
edifVersion
else
enclosureDistance
endType
entry
equal
escape
event
exactly
external
fabricate
false
figure
figureArea
figureGroup
figureGroupObject
figureGroupOverride
figureGroupRef
figurePerimeter
figureWidth
fillPattern
fix
floor
follow
forEach
forbiddenEvent
formal
formalList
generate
globalPortRef
greaterThan
gridMap
if
ignore
includeFigureGroup
increasing
initial
instance
instanceBackAnnotate
instanceGroup
instanceMap
instanceRef
integer
integerDisplay
interFigureGroupSpacing
interface
intersection
intraFigureGroupSpacing
inverse
isolated
iterate
joined
justify
keywordAlias
keywordDefine
keywordDisplay
keywordLevel
keywordMap
keywordParameters
lessThan
library
libraryRef
listOfNets
listOfPorts
literal
loadDelay
logicAssign
logicInput
logicList
logicMapInput
logicMapOutput
logicOneOf
logicOutput
logicPort
logicRef
logicValue
logicWaveform
maintain
match
max
member
miNoMax
miNoMaxDisplay
min
mnm
mod
multipleValueSet
mustJoin
name
negate
net
netBackAnnotate
netBundle
netDelay
netGroup
netMap
netRef
noChange
nonPermutable
not
notAllowed
notchSpacing
number
numberDefinition
numberDisplay
offPageConnector
offsetEvent
openShape
optional
or
orientation
origin
overhangDistance
overlapDistance
oversize
owner
page
pageSize
parameter
parameterAssign
parameterDisplay
path
pathDelay
pathWidth
permutable
physicalDesignRule
plug
point
pointDisplay
pointList
pointSubtract
pointSum
polygon
port
portBackAnnotate
portBundle
portDelay
portGroup
portImplementation
portInstance
portList
portListAlias
portMap
portRef
product
program
property
propertyDisplay
protectionFrame
pt
rangeVector
rectangle
rectangleSize
rename
resolves
scale
scaleX
scaleY
section
shape
simulate
simulationInfo
singleValueSet
site
socket
socketSet
status
steady
strictlyIncreasing
string
stringDisplay
strong
subtract
sum
symbol
symmetry
table
tableDefault
technology
textHeight
then
timeInterval
timeStamp
timing
transform
transition
trigger
true
unconstrained
undefined
union
unit
unused
userData
variable
version
view
viewList
viewMap
viewRef
viewType
visible
voltageMap
waveValue
weak
weakJoined
when
while
written
xCoord
xor
yCoord