prev_cmp_tree_pro.qmsg

用FGGA 原理图的形式输入

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II " "Info: Running Quartus II TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Mar 13 22:38:41 2009 " "Info: Processing started: Fri Mar 13 22:38:41 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta tree_pro -c tree_pro " "Info: Command: quartus_sta tree_pro -c tree_pro" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "0" "" "Info: qsta_default_script.tcl version: 25.0.1.4" {  } {  } 0 0 "qsta_default_script.tcl version: 25.0.1.4" 0 0 "" 0}
{ "Warning" "WSTA_NOT_IN_STA_MODE" "" "Warning: Found USE_TIMEQUEST_TIMING_ANALYZER=OFF. The TimeQuest Timing Analyzer is not the default Timing Analysis Tool during full compilation." {  } {  } 0 0 "Found USE_TIMEQUEST_TIMING_ANALYZER=OFF. The TimeQuest Timing Analyzer is not the default Timing Analysis Tool during full compilation." 0 0 "" 0}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "tree_pro.sdc " "Critical Warning: SDC file not found: 'tree_pro.sdc'. An SDC file is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the compiler will not properly optimize the design" {  } {  } 1 0 "SDC file not found: '%1!s!'. An SDC file is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the compiler will not properly optimize the design" 0 0 "" 0}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "Info: No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 0 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "" 0}
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "Warning: No clocks defined in design." {  } {  } 0 0 "No clocks defined in design." 0 0 "" 0}
{ "Warning" "WSTA_NO_ASSIGNMENTS_TO_REPORT" "report_clocks " "Warning: Command report_clocks could not find any constraints or exceptions to report" {  } {  } 0 0 "Command %1!s! could not find any constraints or exceptions to report" 0 0 "" 0}
{ "Info" "0" "" "Info: Analyzing Slow Model" {  } {  } 0 0 "Analyzing Slow Model" 0 0 "" 0}
{ "Warning" "WSTA_NO_ASSIGNMENTS_TO_REPORT" "report_clock_fmax_summary " "Warning: Command report_clock_fmax_summary could not find any constraints or exceptions to report" {  } {  } 0 0 "Command %1!s! could not find any constraints or exceptions to report" 0 0 "" 0}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "setup " "Info: No setup paths to report" {  } {  } 0 0 "No %1!s! paths to report" 0 0 "" 0}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "hold " "Info: No hold paths to report" {  } {  } 0 0 "No %1!s! paths to report" 0 0 "" 0}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "recovery " "Info: No recovery paths to report" {  } {  } 0 0 "No %1!s! paths to report" 0 0 "" 0}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "removal " "Info: No removal paths to report" {  } {  } 0 0 "No %1!s! paths to report" 0 0 "" 0}
{ "Warning" "WSTA_NO_ASSIGNMENTS_TO_REPORT" "report_min_pulse_width " "Warning: Command report_min_pulse_width could not find any constraints or exceptions to report" {  } {  } 0 0 "Command %1!s! could not find any constraints or exceptions to report" 0 0 "" 0}
{ "Info" "0" "" "Info: Analyzing Fast Model" {  } {  } 0 0 "Analyzing Fast Model" 0 0 "" 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0}
{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "1 " "Warning: Found 1 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "f 0 " "Info: Pin \"f\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0}  } {  } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "" 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "Info: No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 0 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "" 0}
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "Warning: No clocks defined in design." {  } {  } 0 0 "No clocks defined in design." 0 0 "" 0}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "setup " "Info: No setup paths to report" {  } {  } 0 0 "No %1!s! paths to report" 0 0 "" 0}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "hold " "Info: No hold paths to report" {  } {  } 0 0 "No %1!s! paths to report" 0 0 "" 0}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "recovery " "Info: No recovery paths to report" {  } {  } 0 0 "No %1!s! paths to report" 0 0 "" 0}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "removal " "Info: No removal paths to report" {  } {  } 0 0 "No %1!s! paths to report" 0 0 "" 0}
{ "Warning" "WSTA_NO_ASSIGNMENTS_TO_REPORT" "report_min_pulse_width " "Warning: Command report_min_pulse_width could not find any constraints or exceptions to report" {  } {  } 0 0 "Command %1!s! could not find any constraints or exceptions to report" 0 0 "" 0}
{ "Warning" "WSTA_ADVANCED_IO_TIMING_IS_NOT_ENABLED" "" "Warning: Advanced I/O Timing is not enabled" {  } {  } 0 0 "Advanced I/O Timing is not enabled" 0 0 "" 0}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Info: Design is not fully constrained for setup requirements" {  } {  } 0 0 "Design is not fully constrained for %1!s! requirements" 0 0 "" 0}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Info: Design is not fully constrained for hold requirements" {  } {  } 0 0 "Design is not fully constrained for %1!s! requirements" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 10 s Quartus II " "Info: Quartus II TimeQuest Timing Analyzer was successful. 0 errors, 10 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "145 " "Info: Allocated 145 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Fri Mar 13 22:38:46 2009 " "Info: Processing ended: Fri Mar 13 22:38:46 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}