tree_pro.sta.rpt

用FGGA 原理图的形式输入

TimeQuest Timing Analyzer report for tree_pro
Fri Mar 13 22:38:46 2009
Quartus II Version 7.2 Build 151 09/26/2007 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. TimeQuest Timing Analyzer Summary
  3. Clocks
  4. Slow Model Fmax Summary
  5. Slow Model Setup Summary
  6. Slow Model Hold Summary
  7. Slow Model Recovery Summary
  8. Slow Model Removal Summary
  9. Slow Model Minimum Pulse Width
 10. Fast Model Setup Summary
 11. Fast Model Hold Summary
 12. Fast Model Recovery Summary
 13. Fast Model Removal Summary
 14. Fast Model Minimum Pulse Width
 15. Clock Transfers
 16. Report TCCS
 17. Report RSKM
 18. Unconstrained Paths
 19. TimeQuest Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-----------------------------------------------------------------------+
; TimeQuest Timing Analyzer Summary                                     ;
+--------------------+--------------------------------------------------+
; Quartus II Version ; Version 7.2 Build 151 09/26/2007 SJ Full Version ;
; Revision Name      ; tree_pro                                         ;
; Device Family      ; Cyclone II                                       ;
; Device Name        ; EP2C35F672C6                                     ;
; Timing Models      ; Final                                            ;
; Delay Model        ; Combined                                         ;
; Rise/Fall Delays   ; Unavailable                                      ;
+--------------------+--------------------------------------------------+


----------
; Clocks ;
----------
No clocks to report.


---------------------------
; Slow Model Fmax Summary ;
---------------------------
No paths to report.


----------------------------
; Slow Model Setup Summary ;
----------------------------
No paths to report.


---------------------------
; Slow Model Hold Summary ;
---------------------------
No paths to report.


-------------------------------
; Slow Model Recovery Summary ;
-------------------------------
No paths to report.


------------------------------
; Slow Model Removal Summary ;
------------------------------
No paths to report.


----------------------------------
; Slow Model Minimum Pulse Width ;
----------------------------------
Nothing to report.


----------------------------
; Fast Model Setup Summary ;
----------------------------
No paths to report.


---------------------------
; Fast Model Hold Summary ;
---------------------------
No paths to report.


-------------------------------
; Fast Model Recovery Summary ;
-------------------------------
No paths to report.


------------------------------
; Fast Model Removal Summary ;
------------------------------
No paths to report.


----------------------------------
; Fast Model Minimum Pulse Width ;
----------------------------------
Nothing to report.


-------------------
; Clock Transfers ;
-------------------
No clock transfers to report.


---------------
; Report TCCS ;
---------------
No LVDS transmitter found in design.


---------------
; Report RSKM ;
---------------
No LVDS receiver found in design.


+------------------------------------------------+
; Unconstrained Paths                            ;
+---------------------------------+-------+------+
; Property                        ; Setup ; Hold ;
+---------------------------------+-------+------+
; Illegal Clocks                  ; 0     ; 0    ;
; Unconstrained Clocks            ; 0     ; 0    ;
; Unconstrained Input Ports       ; 2     ; 2    ;
; Unconstrained Input Port Paths  ; 2     ; 2    ;
; Unconstrained Output Ports      ; 0     ; 0    ;
; Unconstrained Output Port Paths ; 0     ; 0    ;
+---------------------------------+-------+------+


+------------------------------------+
; TimeQuest Timing Analyzer Messages ;
+------------------------------------+
Info: *******************************************************************
Info: Running Quartus II TimeQuest Timing Analyzer
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Fri Mar 13 22:38:41 2009
Info: Command: quartus_sta tree_pro -c tree_pro
Info: qsta_default_script.tcl version: 25.0.1.4
Warning: Found USE_TIMEQUEST_TIMING_ANALYZER=OFF. The TimeQuest Timing Analyzer is not the default Timing Analysis Tool during full compilation.
Critical Warning: SDC file not found: 'tree_pro.sdc'. An SDC file is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the compiler will not properly optimize the design
Info: No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
Warning: No clocks defined in design.
Warning: Command report_clocks could not find any constraints or exceptions to report
Info: Analyzing Slow Model
Warning: Command report_clock_fmax_summary could not find any constraints or exceptions to report
Info: No setup paths to report
Info: No hold paths to report
Info: No recovery paths to report
Info: No removal paths to report
Warning: Command report_min_pulse_width could not find any constraints or exceptions to report
Info: Analyzing Fast Model
Info: Started post-fitting delay annotation
Warning: Found 1 output pins without output pin load capacitance assignment
    Info: Pin "f" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Delay annotation completed successfully
Info: No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
Warning: No clocks defined in design.
Info: No setup paths to report
Info: No hold paths to report
Info: No recovery paths to report
Info: No removal paths to report
Warning: Command report_min_pulse_width could not find any constraints or exceptions to report
Warning: Advanced I/O Timing is not enabled
Info: Design is not fully constrained for setup requirements
Info: Design is not fully constrained for hold requirements
Info: Quartus II TimeQuest Timing Analyzer was successful. 0 errors, 10 warnings
    Info: Allocated 145 megabytes of memory during processing
    Info: Processing ended: Fri Mar 13 22:38:46 2009
    Info: Elapsed time: 00:00:05