📄 ledwater.map.rpt
字号:
Analysis & Synthesis report for ledwater
Sat Feb 18 13:30:20 2006
Version 5.0 Build 148 04/26/2005 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Analysis & Synthesis Source Files Read
5. Analysis & Synthesis Resource Usage Summary
6. Analysis & Synthesis Resource Utilization by Entity
7. General Register Statistics
8. Inverted Register Statistics
9. Analysis & Synthesis Equations
10. Analysis & Synthesis Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-----------------------------+------------------------------------------+
; Analysis & Synthesis Status ; Successful - Sat Feb 18 13:30:20 2006 ;
; Quartus II Version ; 5.0 Build 148 04/26/2005 SJ Full Version ;
; Revision Name ; ledwater ;
; Top-level Entity Name ; ledwater ;
; Family ; MAX II ;
; Total logic elements ; 43 ;
; Total pins ; 14 ;
; Total virtual pins ; 0 ;
; UFM blocks ; 0 ;
+-----------------------------+------------------------------------------+
+----------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+--------------------------------------------------------------------+---------------+---------------+
; Option ; Setting ; Default Value ;
+--------------------------------------------------------------------+---------------+---------------+
; Device ; EPM1270T144C5 ; ;
; Top-level entity name ; ledwater ; ledwater ;
; Family name ; MAX II ; Stratix ;
; Use smart compilation ; Off ; Off ;
; Restructure Multiplexers ; Auto ; Auto ;
; Create Debugging Nodes for IP Cores ; off ; off ;
; Preserve fewer node names ; On ; On ;
; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; VHDL Version ; VHDL93 ; VHDL93 ;
; State Machine Processing ; Auto ; Auto ;
; Extract Verilog State Machines ; On ; On ;
; Extract VHDL State Machines ; On ; On ;
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
; NOT Gate Push-Back ; On ; On ;
; Power-Up Don't Care ; On ; On ;
; Remove Redundant Logic Cells ; Off ; Off ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore LCELL Buffers ; Off ; Off ;
; Ignore SOFT Buffers ; On ; On ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Optimization Technique -- MAX II ; Balanced ; Balanced ;
; Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II ; 70 ; 70 ;
; Auto Carry Chains ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Remove Duplicate Logic ; On ; On ;
; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
; Perform gate-level register retiming ; Off ; Off ;
; Allow register retiming to trade off Tsu/Tco with Fmax ; On ; On ;
; Auto Shift Register Replacement ; On ; On ;
; Auto Clock Enable Replacement ; On ; On ;
; Allows Synchronous Control Signal Usage in Normal Mode Logic Cells ; On ; On ;
; Auto RAM Block Balancing ; On ; On ;
; Auto Resource Sharing ; Off ; Off ;
; Maximum Number of M512 Memory Blocks ; -1 ; -1 ;
; Maximum Number of M4K Memory Blocks ; -1 ; -1 ;
; Maximum Number of M-RAM Memory Blocks ; -1 ; -1 ;
; Ignore translate_off and translate_on Synthesis Directives ; Off ; Off ;
; Show Parameter Settings Tables in Synthesis Report ; On ; On ;
+--------------------------------------------------------------------+---------------+---------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+------------------------+------------------------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
+----------------------------------+-----------------+------------------------+------------------------------------------------------------------------------------+
; ledwater.v ; yes ; User Verilog HDL File ; E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/ledwater.v ;
+----------------------------------+-----------------+------------------------+------------------------------------------------------------------------------------+
+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+-----------------------------------+---------+
; Resource ; Usage ;
+-----------------------------------+---------+
; Total logic elements ; 43 ;
; Total combinational functions ; 31 ;
; -- Total 4-input functions ; 7 ;
; -- Total 3-input functions ; 0 ;
; -- Total 2-input functions ; 1 ;
; -- Total 1-input functions ; 23 ;
; -- Total 0-input functions ; 0 ;
; Combinational cells for routing ; 0 ;
; Total registers ; 35 ;
; Total logic cells in carry chains ; 23 ;
; I/O pins ; 14 ;
; Maximum fan-out node ; clk ;
; Maximum fan-out ; 35 ;
; Total fan-out ; 181 ;
; Average fan-out ; 3.18 ;
+-----------------------------------+---------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
; |ledwater ; 43 (43) ; 35 ; 0 ; 14 ; 0 ; 8 (8) ; 12 (12) ; 23 (23) ; 23 (23) ; |ledwater ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 35 ;
; Number of registers using Synchronous Clear ; 0 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 35 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 12 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+---------------------------------------------------+
; Inverted Register Statistics ;
+-----------------------------------------+---------+
; Inverted Register ; Fan out ;
+-----------------------------------------+---------+
; dataout[0]~reg0 ; 2 ;
; dataout[1]~reg0 ; 2 ;
; dataout[2]~reg0 ; 2 ;
; dataout[3]~reg0 ; 2 ;
; dataout[4]~reg0 ; 2 ;
; dataout[7]~reg0 ; 2 ;
; dataout[8]~reg0 ; 2 ;
; dataout[9]~reg0 ; 2 ;
; dataout[10]~reg0 ; 2 ;
; dataout[11]~reg0 ; 2 ;
; Total number of inverted registers = 10 ; ;
+-----------------------------------------+---------+
+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/ledwater.map.eqn.
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
Info: Processing started: Sat Feb 18 13:30:18 2006
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ledwater -c ledwater
Info: Found 1 design units, including 1 entities, in source file ledwater.v
Info: Found entity 1: ledwater
Info: Elaborating entity "ledwater" for the top level hierarchy
Warning: Verilog HDL assignment warning at ledwater.v(15): truncated value with size 32 to match size of target (23)
Warning: Verilog HDL assignment warning at ledwater.v(19): truncated value with size 32 to match size of target (23)
Info: Registers with preset signals will power-up high
Info: Implemented 57 device resources after synthesis - the final resource count might be different
Info: Implemented 2 input pins
Info: Implemented 12 output pins
Info: Implemented 43 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings
Info: Processing ended: Sat Feb 18 13:30:20 2006
Info: Elapsed time: 00:00:03
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -