ledwater.tan.qmsg

跑马灯LED程序,实现流水灯显示

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "ledwater.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/ledwater.v" 6 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register cnt\[19\] register dataout\[11\]~reg0 122.25 MHz 8.18 ns Internal " "Info: Clock \"clk\" has Internal fmax of 122.25 MHz between source register \"cnt\[19\]\" and destination register \"dataout\[11\]~reg0\" (period= 8.18 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.471 ns + Longest register register " "Info: + Longest register to register delay is 7.471 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cnt\[19\] 1 REG LC_X6_Y6_N3 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X6_Y6_N3; Fanout = 4; REG Node = 'cnt\[19\]'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/db/ledwater_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/db/ledwater_cmp.qrpt" Compiler "ledwater" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/db/ledwater.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/" "" "" { cnt[19] } "NODE_NAME" } "" } } { "ledwater.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/ledwater.v" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.909 ns) + CELL(0.914 ns) 1.823 ns reduce_nor~180 2 COMB LC_X6_Y6_N7 1 " "Info: 2: + IC(0.909 ns) + CELL(0.914 ns) = 1.823 ns; Loc. = LC_X6_Y6_N7; Fanout = 1; COMB Node = 'reduce_nor~180'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/db/ledwater_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/db/ledwater_cmp.qrpt" Compiler "ledwater" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/db/ledwater.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/" "" "1.823 ns" { cnt[19] reduce_nor~180 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.868 ns) + CELL(0.200 ns) 3.891 ns reduce_nor~181 3 COMB LC_X5_Y5_N7 1 " "Info: 3: + IC(1.868 ns) + CELL(0.200 ns) = 3.891 ns; Loc. = LC_X5_Y5_N7; Fanout = 1; COMB Node = 'reduce_nor~181'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/db/ledwater_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/db/ledwater_cmp.qrpt" Compiler "ledwater" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/db/ledwater.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/" "" "2.068 ns" { reduce_nor~180 reduce_nor~181 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.759 ns) + CELL(0.511 ns) 5.161 ns reduce_nor~0 4 COMB LC_X5_Y5_N4 12 " "Info: 4: + IC(0.759 ns) + CELL(0.511 ns) = 5.161 ns; Loc. = LC_X5_Y5_N4; Fanout = 12; COMB Node = 'reduce_nor~0'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/db/ledwater_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/db/ledwater_cmp.qrpt" Compiler "ledwater" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/db/ledwater.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/" "" "1.270 ns" { reduce_nor~181 reduce_nor~0 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.067 ns) + CELL(1.243 ns) 7.471 ns dataout\[11\]~reg0 5 REG LC_X4_Y5_N3 2 " "Info: 5: + IC(1.067 ns) + CELL(1.243 ns) = 7.471 ns; Loc. = LC_X4_Y5_N3; Fanout = 2; REG Node = 'dataout\[11\]~reg0'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/db/ledwater_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/db/ledwater_cmp.qrpt" Compiler "ledwater" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/db/ledwater.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/" "" "2.310 ns" { reduce_nor~0 dataout[11]~reg0 } "NODE_NAME" } "" } } { "ledwater.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/ledwater.v" 14 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.868 ns 38.39 % " "Info: Total cell delay = 2.868 ns ( 38.39 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.603 ns 61.61 % " "Info: Total interconnect delay = 4.603 ns ( 61.61 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/db/ledwater_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/db/ledwater_cmp.qrpt" Compiler "ledwater" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/db/ledwater.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/" "" "7.471 ns" { cnt[19] reduce_nor~180 reduce_nor~181 reduce_nor~0 dataout[11]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "7.471 ns" { cnt[19] reduce_nor~180 reduce_nor~181 reduce_nor~0 dataout[11]~reg0 } { 0.000ns 0.909ns 1.868ns 0.759ns 1.067ns } { 0.000ns 0.914ns 0.200ns 0.511ns 1.243ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 6.720 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 6.720 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns clk 1 CLK PIN_127 35 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_127; Fanout = 35; CLK Node = 'clk'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/db/ledwater_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/db/ledwater_cmp.qrpt" Compiler "ledwater" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/db/ledwater.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/" "" "" { clk } "NODE_NAME" } "" } } { "ledwater.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/ledwater.v" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.670 ns) + CELL(0.918 ns) 6.720 ns dataout\[11\]~reg0 2 REG LC_X4_Y5_N3 2 " "Info: 2: + IC(4.670 ns) + CELL(0.918 ns) = 6.720 ns; Loc. = LC_X4_Y5_N3; Fanout = 2; REG Node = 'dataout\[11\]~reg0'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/db/ledwater_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/db/ledwater_cmp.qrpt" Compiler "ledwater" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/db/ledwater.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/" "" "5.588 ns" { clk dataout[11]~reg0 } "NODE_NAME" } "" } } { "ledwater.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/ledwater.v" 14 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.050 ns 30.51 % " "Info: Total cell delay = 2.050 ns ( 30.51 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.670 ns 69.49 % " "Info: Total interconnect delay = 4.670 ns ( 69.49 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/db/ledwater_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/db/ledwater_cmp.qrpt" Compiler "ledwater" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/db/ledwater.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/" "" "6.720 ns" { clk dataout[11]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.720 ns" { clk clk~combout dataout[11]~reg0 } { 0.000ns 0.000ns 4.670ns } { 0.000ns 1.132ns 0.918ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 6.720 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 6.720 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns clk 1 CLK PIN_127 35 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_127; Fanout = 35; CLK Node = 'clk'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/db/ledwater_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/db/ledwater_cmp.qrpt" Compiler "ledwater" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/db/ledwater.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/" "" "" { clk } "NODE_NAME" } "" } } { "ledwater.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/ledwater.v" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.670 ns) + CELL(0.918 ns) 6.720 ns cnt\[19\] 2 REG LC_X6_Y6_N3 4 " "Info: 2: + IC(4.670 ns) + CELL(0.918 ns) = 6.720 ns; Loc. = LC_X6_Y6_N3; Fanout = 4; REG Node = 'cnt\[19\]'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/db/ledwater_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/db/ledwater_cmp.qrpt" Compiler "ledwater" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/db/ledwater.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/" "" "5.588 ns" { clk cnt[19] } "NODE_NAME" } "" } } { "ledwater.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/ledwater.v" 10 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.050 ns 30.51 % " "Info: Total cell delay = 2.050 ns ( 30.51 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.670 ns 69.49 % " "Info: Total interconnect delay = 4.670 ns ( 69.49 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/db/ledwater_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/db/ledwater_cmp.qrpt" Compiler "ledwater" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/db/ledwater.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/" "" "6.720 ns" { clk cnt[19] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.720 ns" { clk clk~combout cnt[19] } { 0.000ns 0.000ns 4.670ns } { 0.000ns 1.132ns 0.918ns } } }  } 0}  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/db/ledwater_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/db/ledwater_cmp.qrpt" Compiler "ledwater" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/db/ledwater.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/" "" "6.720 ns" { clk dataout[11]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.720 ns" { clk clk~combout dataout[11]~reg0 } { 0.000ns 0.000ns 4.670ns } { 0.000ns 1.132ns 0.918ns } } } { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/db/ledwater_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/db/ledwater_cmp.qrpt" Compiler "ledwater" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/db/ledwater.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/" "" "6.720 ns" { clk cnt[19] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.720 ns" { clk clk~combout cnt[19] } { 0.000ns 0.000ns 4.670ns } { 0.000ns 1.132ns 0.918ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "ledwater.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/ledwater.v" 10 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "ledwater.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/ledwater.v" 14 -1 0 } }  } 0}  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/db/ledwater_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/db/ledwater_cmp.qrpt" Compiler "ledwater" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/db/ledwater.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/" "" "7.471 ns" { cnt[19] reduce_nor~180 reduce_nor~181 reduce_nor~0 dataout[11]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "7.471 ns" { cnt[19] reduce_nor~180 reduce_nor~181 reduce_nor~0 dataout[11]~reg0 } { 0.000ns 0.909ns 1.868ns 0.759ns 1.067ns } { 0.000ns 0.914ns 0.200ns 0.511ns 1.243ns } } } { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/db/ledwater_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/db/ledwater_cmp.qrpt" Compiler "ledwater" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/db/ledwater.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/" "" "6.720 ns" { clk dataout[11]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.720 ns" { clk clk~combout dataout[11]~reg0 } { 0.000ns 0.000ns 4.670ns } { 0.000ns 1.132ns 0.918ns } } } { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/db/ledwater_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/db/ledwater_cmp.qrpt" Compiler "ledwater" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/db/ledwater.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/" "" "6.720 ns" { clk cnt[19] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.720 ns" { clk clk~combout cnt[19] } { 0.000ns 0.000ns 4.670ns } { 0.000ns 1.132ns 0.918ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk dataout\[0\] dataout\[0\]~reg0 12.003 ns register " "Info: tco from clock \"clk\" to destination pin \"dataout\[0\]\" through register \"dataout\[0\]~reg0\" is 12.003 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 6.720 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 6.720 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns clk 1 CLK PIN_127 35 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_127; Fanout = 35; CLK Node = 'clk'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/db/ledwater_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/db/ledwater_cmp.qrpt" Compiler "ledwater" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/db/ledwater.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/" "" "" { clk } "NODE_NAME" } "" } } { "ledwater.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/ledwater.v" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.670 ns) + CELL(0.918 ns) 6.720 ns dataout\[0\]~reg0 2 REG LC_X5_Y5_N9 2 " "Info: 2: + IC(4.670 ns) + CELL(0.918 ns) = 6.720 ns; Loc. = LC_X5_Y5_N9; Fanout = 2; REG Node = 'dataout\[0\]~reg0'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/db/ledwater_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/db/ledwater_cmp.qrpt" Compiler "ledwater" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/db/ledwater.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/" "" "5.588 ns" { clk dataout[0]~reg0 } "NODE_NAME" } "" } } { "ledwater.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/ledwater.v" 14 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.050 ns 30.51 % " "Info: Total cell delay = 2.050 ns ( 30.51 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.670 ns 69.49 % " "Info: Total interconnect delay = 4.670 ns ( 69.49 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/db/ledwater_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/db/ledwater_cmp.qrpt" Compiler "ledwater" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/db/ledwater.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/" "" "6.720 ns" { clk dataout[0]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.720 ns" { clk clk~combout dataout[0]~reg0 } { 0.000ns 0.000ns 4.670ns } { 0.000ns 1.132ns 0.918ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "ledwater.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/ledwater.v" 14 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.907 ns + Longest register pin " "Info: + Longest register to pin delay is 4.907 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns dataout\[0\]~reg0 1 REG LC_X5_Y5_N9 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X5_Y5_N9; Fanout = 2; REG Node = 'dataout\[0\]~reg0'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/db/ledwater_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/db/ledwater_cmp.qrpt" Compiler "ledwater" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/db/ledwater.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/" "" "" { dataout[0]~reg0 } "NODE_NAME" } "" } } { "ledwater.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/ledwater.v" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.585 ns) + CELL(2.322 ns) 4.907 ns dataout\[0\] 2 PIN PIN_55 0 " "Info: 2: + IC(2.585 ns) + CELL(2.322 ns) = 4.907 ns; Loc. = PIN_55; Fanout = 0; PIN Node = 'dataout\[0\]'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/db/ledwater_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/db/ledwater_cmp.qrpt" Compiler "ledwater" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/db/ledwater.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/" "" "4.907 ns" { dataout[0]~reg0 dataout[0] } "NODE_NAME" } "" } } { "ledwater.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/ledwater.v" 7 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.322 ns 47.32 % " "Info: Total cell delay = 2.322 ns ( 47.32 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.585 ns 52.68 % " "Info: Total interconnect delay = 2.585 ns ( 52.68 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/db/ledwater_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/db/ledwater_cmp.qrpt" Compiler "ledwater" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/db/ledwater.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/" "" "4.907 ns" { dataout[0]~reg0 dataout[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "4.907 ns" { dataout[0]~reg0 dataout[0] } { 0.000ns 2.585ns } { 0.000ns 2.322ns } } }  } 0}  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/db/ledwater_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/db/ledwater_cmp.qrpt" Compiler "ledwater" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/db/ledwater.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/" "" "6.720 ns" { clk dataout[0]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.720 ns" { clk clk~combout dataout[0]~reg0 } { 0.000ns 0.000ns 4.670ns } { 0.000ns 1.132ns 0.918ns } } } { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/db/ledwater_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/db/ledwater_cmp.qrpt" Compiler "ledwater" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/db/ledwater.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/" "" "4.907 ns" { dataout[0]~reg0 dataout[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "4.907 ns" { dataout[0]~reg0 dataout[0] } { 0.000ns 2.585ns } { 0.000ns 2.322ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Feb 18 13:30:33 2006 " "Info: Processing ended: Sat Feb 18 13:30:33 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}