ledwater.map.qmsg

跑马灯LED程序,实现流水灯显示

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Feb 18 13:30:18 2006 " "Info: Processing started: Sat Feb 18 13:30:18 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ledwater -c ledwater " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ledwater -c ledwater" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ledwater.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ledwater.v" { { "Info" "ISGN_ENTITY_NAME" "1 ledwater " "Info: Found entity 1: ledwater" {  } { { "ledwater.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/ledwater.v" 4 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "ledwater " "Info: Elaborating entity \"ledwater\" for the top level hierarchy" {  } {  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 23 ledwater.v(15) " "Warning: Verilog HDL assignment warning at ledwater.v(15): truncated value with size 32 to match size of target (23)" {  } { { "ledwater.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/ledwater.v" 15 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 23 ledwater.v(19) " "Warning: Verilog HDL assignment warning at ledwater.v(19): truncated value with size 32 to match size of target (23)" {  } { { "ledwater.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/ledwater.v" 19 0 0 } }  } 0}
{ "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "ledwater.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/ledwater.v" 7 -1 0 } } { "ledwater.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/ledwater.v" 7 -1 0 } } { "ledwater.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/ledwater.v" 7 -1 0 } } { "ledwater.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/ledwater.v" 7 -1 0 } } { "ledwater.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/ledwater.v" 7 -1 0 } } { "ledwater.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/ledwater.v" 7 -1 0 } } { "ledwater.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/ledwater.v" 7 -1 0 } } { "ledwater.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/ledwater.v" 7 -1 0 } } { "ledwater.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/ledwater.v" 7 -1 0 } } { "ledwater.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/跑马灯/ledwater.v" 7 -1 0 } }  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "57 " "Info: Implemented 57 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "12 " "Info: Implemented 12 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "43 " "Info: Implemented 43 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 2 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Feb 18 13:30:20 2006 " "Info: Processing ended: Sat Feb 18 13:30:20 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0}  } {  } 0}