ledwater.tan.rpt

跑马灯LED程序,实现流水灯显示

; N/A                                     ; 141.98 MHz ( period = 7.043 ns )                    ; cnt[6]  ; dataout[8]~reg0  ; clk        ; clk      ; None                        ; None                      ; 6.334 ns                ;
; N/A                                     ; 141.98 MHz ( period = 7.043 ns )                    ; cnt[6]  ; dataout[7]~reg0  ; clk        ; clk      ; None                        ; None                      ; 6.334 ns                ;
; N/A                                     ; 141.98 MHz ( period = 7.043 ns )                    ; cnt[6]  ; dataout[6]~reg0  ; clk        ; clk      ; None                        ; None                      ; 6.334 ns                ;
; N/A                                     ; 141.98 MHz ( period = 7.043 ns )                    ; cnt[6]  ; dataout[3]~reg0  ; clk        ; clk      ; None                        ; None                      ; 6.334 ns                ;
; N/A                                     ; 141.98 MHz ( period = 7.043 ns )                    ; cnt[6]  ; dataout[0]~reg0  ; clk        ; clk      ; None                        ; None                      ; 6.334 ns                ;
; N/A                                     ; 142.84 MHz ( period = 7.001 ns )                    ; cnt[4]  ; dataout[10]~reg0 ; clk        ; clk      ; None                        ; None                      ; 6.292 ns                ;
; N/A                                     ; 142.84 MHz ( period = 7.001 ns )                    ; cnt[4]  ; dataout[9]~reg0  ; clk        ; clk      ; None                        ; None                      ; 6.292 ns                ;
; N/A                                     ; 142.84 MHz ( period = 7.001 ns )                    ; cnt[4]  ; dataout[8]~reg0  ; clk        ; clk      ; None                        ; None                      ; 6.292 ns                ;
; N/A                                     ; 142.84 MHz ( period = 7.001 ns )                    ; cnt[4]  ; dataout[7]~reg0  ; clk        ; clk      ; None                        ; None                      ; 6.292 ns                ;
; N/A                                     ; 142.84 MHz ( period = 7.001 ns )                    ; cnt[4]  ; dataout[6]~reg0  ; clk        ; clk      ; None                        ; None                      ; 6.292 ns                ;
; N/A                                     ; 142.84 MHz ( period = 7.001 ns )                    ; cnt[4]  ; dataout[3]~reg0  ; clk        ; clk      ; None                        ; None                      ; 6.292 ns                ;
; N/A                                     ; 142.84 MHz ( period = 7.001 ns )                    ; cnt[4]  ; dataout[0]~reg0  ; clk        ; clk      ; None                        ; None                      ; 6.292 ns                ;
; N/A                                     ; 143.70 MHz ( period = 6.959 ns )                    ; cnt[10] ; dataout[11]~reg0 ; clk        ; clk      ; None                        ; None                      ; 6.250 ns                ;
; N/A                                     ; 143.70 MHz ( period = 6.959 ns )                    ; cnt[10] ; dataout[5]~reg0  ; clk        ; clk      ; None                        ; None                      ; 6.250 ns                ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;         ;                  ;            ;          ;                             ;                           ;                         ;
+-----------------------------------------+-----------------------------------------------------+---------+------------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+---------------------------------------------------------------------------------+
; tco                                                                             ;
+-------+--------------+------------+------------------+-------------+------------+
; Slack ; Required tco ; Actual tco ; From             ; To          ; From Clock ;
+-------+--------------+------------+------------------+-------------+------------+
; N/A   ; None         ; 12.003 ns  ; dataout[0]~reg0  ; dataout[0]  ; clk        ;
; N/A   ; None         ; 11.970 ns  ; dataout[7]~reg0  ; dataout[7]  ; clk        ;
; N/A   ; None         ; 11.877 ns  ; dataout[11]~reg0 ; dataout[11] ; clk        ;
; N/A   ; None         ; 11.859 ns  ; dataout[5]~reg0  ; dataout[5]  ; clk        ;
; N/A   ; None         ; 11.855 ns  ; dataout[8]~reg0  ; dataout[8]  ; clk        ;
; N/A   ; None         ; 11.845 ns  ; dataout[1]~reg0  ; dataout[1]  ; clk        ;
; N/A   ; None         ; 11.837 ns  ; dataout[6]~reg0  ; dataout[6]  ; clk        ;
; N/A   ; None         ; 11.470 ns  ; dataout[10]~reg0 ; dataout[10] ; clk        ;
; N/A   ; None         ; 11.454 ns  ; dataout[3]~reg0  ; dataout[3]  ; clk        ;
; N/A   ; None         ; 11.447 ns  ; dataout[4]~reg0  ; dataout[4]  ; clk        ;
; N/A   ; None         ; 11.427 ns  ; dataout[2]~reg0  ; dataout[2]  ; clk        ;
; N/A   ; None         ; 11.323 ns  ; dataout[9]~reg0  ; dataout[9]  ; clk        ;
+-------+--------------+------------+------------------+-------------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Sat Feb 18 13:30:32 2006
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off ledwater -c ledwater
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 122.25 MHz between source register "cnt[19]" and destination register "dataout[11]~reg0" (period= 8.18 ns)
    Info: + Longest register to register delay is 7.471 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X6_Y6_N3; Fanout = 4; REG Node = 'cnt[19]'
        Info: 2: + IC(0.909 ns) + CELL(0.914 ns) = 1.823 ns; Loc. = LC_X6_Y6_N7; Fanout = 1; COMB Node = 'reduce_nor~180'
        Info: 3: + IC(1.868 ns) + CELL(0.200 ns) = 3.891 ns; Loc. = LC_X5_Y5_N7; Fanout = 1; COMB Node = 'reduce_nor~181'
        Info: 4: + IC(0.759 ns) + CELL(0.511 ns) = 5.161 ns; Loc. = LC_X5_Y5_N4; Fanout = 12; COMB Node = 'reduce_nor~0'
        Info: 5: + IC(1.067 ns) + CELL(1.243 ns) = 7.471 ns; Loc. = LC_X4_Y5_N3; Fanout = 2; REG Node = 'dataout[11]~reg0'
        Info: Total cell delay = 2.868 ns ( 38.39 % )
        Info: Total interconnect delay = 4.603 ns ( 61.61 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 6.720 ns
            Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_127; Fanout = 35; CLK Node = 'clk'
            Info: 2: + IC(4.670 ns) + CELL(0.918 ns) = 6.720 ns; Loc. = LC_X4_Y5_N3; Fanout = 2; REG Node = 'dataout[11]~reg0'
            Info: Total cell delay = 2.050 ns ( 30.51 % )
            Info: Total interconnect delay = 4.670 ns ( 69.49 % )
        Info: - Longest clock path from clock "clk" to source register is 6.720 ns
            Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_127; Fanout = 35; CLK Node = 'clk'
            Info: 2: + IC(4.670 ns) + CELL(0.918 ns) = 6.720 ns; Loc. = LC_X6_Y6_N3; Fanout = 4; REG Node = 'cnt[19]'
            Info: Total cell delay = 2.050 ns ( 30.51 % )
            Info: Total interconnect delay = 4.670 ns ( 69.49 % )
    Info: + Micro clock to output delay of source is 0.376 ns
    Info: + Micro setup delay of destination is 0.333 ns
Info: tco from clock "clk" to destination pin "dataout[0]" through register "dataout[0]~reg0" is 12.003 ns
    Info: + Longest clock path from clock "clk" to source register is 6.720 ns
        Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_127; Fanout = 35; CLK Node = 'clk'
        Info: 2: + IC(4.670 ns) + CELL(0.918 ns) = 6.720 ns; Loc. = LC_X5_Y5_N9; Fanout = 2; REG Node = 'dataout[0]~reg0'
        Info: Total cell delay = 2.050 ns ( 30.51 % )
        Info: Total interconnect delay = 4.670 ns ( 69.49 % )
    Info: + Micro clock to output delay of source is 0.376 ns
    Info: + Longest register to pin delay is 4.907 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X5_Y5_N9; Fanout = 2; REG Node = 'dataout[0]~reg0'
        Info: 2: + IC(2.585 ns) + CELL(2.322 ns) = 4.907 ns; Loc. = PIN_55; Fanout = 0; PIN Node = 'dataout[0]'
        Info: Total cell delay = 2.322 ns ( 47.32 % )
        Info: Total interconnect delay = 2.585 ns ( 52.68 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Sat Feb 18 13:30:33 2006
    Info: Elapsed time: 00:00:02