top_init.c

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    pclk_freq                  = GET_CPU_ClkFreq();             /* Get the UART input clock frequency */

//----------------------------------------------------------------    
    AT91C_BASE_PIOA->PIO_PDR  |= BSP_GPIOA_DBG;                 /* Set GPIOA pins 9 and 10 as DBGU UART pins */
    AT91C_BASE_PIOA->PIO_ASR  |= BSP_GPIOA_DBG;                 /* Select GPIOA attached peripheral (DBGU)   */

    AT91C_BASE_DBGU->DBGU_IDR  = AT91C_US_TXRDY ;               /* Disable Tx interrupts*/
    AT91C_BASE_DBGU->DBGU_IER =   AT91C_US_RXRDY ;                                                               

    AT91C_BASE_DBGU->DBGU_CR   = AT91C_US_RXEN                  /* Enable the receiver  */
                               | AT91C_US_TXEN;                 /* Enable the transmitter */
    AT91C_BASE_DBGU->DBGU_MR   =  AT91C_US_USMODE_NORMAL        /* RS232C mode selected */
                               | AT91C_US_CLKS_CLOCK            /* USART input CLK is MCK */
                               | AT91C_US_CHRL_8_BITS           /* 8 bit data to be sent */
                               | AT91C_US_PAR_NONE              /* No parity bit selected */
                               | AT91C_US_NBSTOP_1_BIT;         /* 1 stop bit selected */                                  

                                                                /* Set the DBGU baud rate */
    AT91C_BASE_DBGU->DBGU_BRGR = (CPU_INT16U)((pclk_freq) /baud_rate / 16);

    AT91C_BASE_PMC->PMC_PCER   = (1 << AT91C_ID_SYS);           /* Enable the DBGU peripheral clock */
   
   /*  AIC interrupt initializing for UART DBGU unit  */
       
   AT91C_BASE_AIC->AIC_IDCR              |= (0x1 << AT91C_ID_SYS);           /*disabling interrupts .*/
   AT91C_BASE_AIC->AIC_SVR[(CPU_INT32U)1] = (CPU_INT32U)UART_DBGU_handler  ; /*passing the handler address. */
   AT91C_BASE_AIC->AIC_SMR[(CPU_INT32U)1] = 0X00000005;                      /* +ve edge  TRIGGER AND PRIORITY 6 (ITS given highets priority). */
   AT91C_BASE_AIC->AIC_IECR              |= (0x1 << AT91C_ID_SYS);           /*Enable interrupts */

 

  /*----------------------------------------------------------------*/    
                                                                /* Set GPIOA pins 0 & 1 as US0 pins*/
    AT91C_BASE_PIOA->PIO_PDR   = BSP_GPIOA_UART0;
    AT91C_BASE_PIOA->PIO_PDR   = BSP_GPIOA_UART0;

                                                                /* ---------------------- SETUP US0 ----------------------- */
    AT91C_BASE_US0->US_IDR     = AT91C_US_TXRDY;                 /* Disable Tx interrupts */
                              
    AT91C_BASE_US0->US_IER =   AT91C_US_RXRDY ;

    AT91C_BASE_US0->US_CR      = AT91C_US_RXEN                  /* Enable the receiver */
                               | AT91C_US_TXEN;                 /* Enable the transmitter */

    AT91C_BASE_US0->US_MR      = AT91C_US_USMODE_NORMAL         /* RS232C mode selected */
                               | AT91C_US_CLKS_CLOCK            /* USART input CLK is MCK */
                               | AT91C_US_CHRL_8_BITS           /* 8 bit data to be sent */
                               | AT91C_US_PAR_NONE              /* No parity bit selected */
                               | AT91C_US_NBSTOP_1_BIT;         /* 1 stop bit selected */
                            
                                                                /* Set the USART baud rate */
    AT91C_BASE_US0->US_BRGR    = (CPU_INT16U)((pclk_freq) / baud_rate / 16);

                                                                /* ---------------- INITIALIZE AIC FOR US0 ---------------- */
    AT91C_BASE_PMC->PMC_PCER   = (1 << AT91C_ID_US0);           /* Enable the US0 peripheral clock */
   
    /*  AIC interrupt initializing for UART0 */
       
    AT91C_BASE_AIC->AIC_IDCR              |= (0x1 << AT91C_ID_US0);         /*disabling interrupts .*/
    AT91C_BASE_AIC->AIC_SVR[(CPU_INT32U)6] = (CPU_INT32U)UART0_handler  ;   /*passing the handler address.*/
    AT91C_BASE_AIC->AIC_SMR[(CPU_INT32U)6] = 0X00000007;                    /*+ve edge  TRIGGER AND PRIORITY 7 (ITS given highets priority).*/
      
    AT91C_BASE_AIC->AIC_IECR              |= (0x1 << AT91C_ID_US0);         /*Enable interrupts .*/
}
static void UART0_handler( void ){
    CPU_INT32U irq_id;
    char temp0;
    AT91C_BASE_AIC->AIC_IVR = 0  ;                    /*Write the IVR, as required TO CLEAR IT .*/
    irq_id  = AT91C_BASE_AIC->AIC_ISR & 0x1F;         /*Retrieve the ID of the interrupting source   ( PIOA ) */
    AT91C_BASE_AIC->AIC_ICCR |=  (0x01 << irq_id);    /*Clear the current interrupt ( PIOA )*/
  
    temp0 =   (char)AT91C_BASE_US0->US_RHR; 
    temp0++;                                          /*no meaning ,for avoiding compiler warning */
    ISR_flag = UART0_FLAG ;                           /*setting flag for UART0 interrupt*/
   
    AT91C_BASE_AIC->AIC_ICCR |= (0x01 << irq_id);     /*Clear all interrupts from PIOA.*/
}
static void UART_DBGU_handler( void ){
    CPU_INT32U irq_id;
    char temp0; 
    AT91C_BASE_AIC->AIC_IVR = 0  ;                    /*Write the IVR, as required TO CLEAR IT .*/
    irq_id  = AT91C_BASE_AIC->AIC_ISR & 0x1F;         /*Retrieve the ID of the interrupting source   ( PIOA ) */
    AT91C_BASE_AIC->AIC_ICCR |=  (0x01 << irq_id);    /*Clear the current interrupt ( PIOA )*/
  
    temp0 =   (char)AT91C_BASE_DBGU->DBGU_RHR;
    temp0++;                                          /*no meaning ,for avoiding compiler warning */
    ISR_flag = UART_DBGU_FLAG ;                       /*setting flag for UART0 interrupt */
     
    AT91C_BASE_AIC->AIC_ICCR |= (0x01 << irq_id);     /*Clear all interrupts from PIOA.*/
}
/*------------------------------------------------------------------------------*/
CPU_INT32U  GET_CPU_ClkFreq (void)
{
    CPU_INT32U  mckr_css;
    CPU_INT32U  pll_mult;
    CPU_INT32U  pll_div;
    CPU_INT32U  mclk_div;
    CPU_INT32U  cpu_freq;

                                                                /* ------------------ MASTER CLOCK INPUT ------------------ */
    mckr_css = (AT91C_BASE_PMC->PMC_MCKR) & 0x00000003;

    switch (mckr_css) {

        case 0x00:                                              /* Slow clock                                               */
             cpu_freq = BSP_SLOW_XTAL_FREQ;
             break;

        case 0x01:                                              /* Main clock                                               */
             cpu_freq = BSP_MAIN_XTAL_FREQ;
             break;

        case 0x02:                                              /* Reserved                                                 */
             cpu_freq = 0;
             break;

        case 0x03:                                              /* PLL clock                                                */
             pll_mult = (AT91C_BASE_CKGR->CKGR_PLLR & 0x07FF0000) >> 16;
             pll_div  = (AT91C_BASE_CKGR->CKGR_PLLR & 0x000000FF) >>  0;

             if (pll_div == 0) {
                 cpu_freq = 0;                                  /* If PLL divider is zero, then PLL output is zero.         */
             } else if (pll_mult == 0) {
                 cpu_freq = BSP_MAIN_XTAL_FREQ;                 /* If PLL multiplier is zero, then PLL is disabled.         */
             } else {
                 cpu_freq = (BSP_MAIN_XTAL_FREQ / pll_div) * (pll_mult + 1);
             }
             break;
    }
                                                                /* ---------------- MASTER CLOCK PRESCALER ---------------- */
                                                                /* Read the Master Clock divider                            */
    mclk_div = (AT91C_BASE_PMC->PMC_MCKR >> 2) & 0x07;

    mclk_div = 1 << mclk_div;                                   /* Convert 0-7 into 1, 2, 4, 8, 16, 32, or 64               */

    if (mclk_div >= 128) {                                      /* Divider pattern for 128 is reserved                      */
        return (cpu_freq);
    }

    cpu_freq = cpu_freq / mclk_div;

    return (cpu_freq);
}
/*-----------------------------------------------------------------------------*/
void  UART_DBG_WrByte(CPU_INT08U tx_byte)
{
   while ((AT91C_BASE_DBGU->DBGU_CSR & AT91C_US_TXRDY) == 0){  
        ;
    }

    AT91C_BASE_DBGU->DBGU_THR    = tx_byte;


}
/*-----------------------------------------------------------------------------*/
void  UART0_WrByte(CPU_INT08U tx_byte)
{
  while ((AT91C_BASE_US0->US_CSR & AT91C_US_TXRDY) == 0){  
        ;
    }

    AT91C_BASE_US0->US_THR = tx_byte;

}
/*-----------------------------------------------------------------------------*/
/*
void  my_irq_handler (CPU_INT32U  except_id)
{
    CPU_FNCT_VOID   pfnct;
    if (except_id == OS_CPU_ARM_EXCEPT_IRQ) {
        pfnct = (CPU_FNCT_VOID)AT91C_BASE_AIC->AIC_IVR;         // Read the interrupt vector from the VIC                   

        while (pfnct != (CPU_FNCT_VOID)0) {                     // Make sure we don't have a NULL pointer                  

          (*pfnct)();                                           // Execute the ISR for the interrupting device             
            AT91C_BASE_AIC->AIC_EOICR = 0;                      // End of handler                                           
            pfnct = (CPU_FNCT_VOID)(AT91C_BASE_AIC->AIC_IVR);   // Read IRQ hanlder from the AIC                           
        }

        AT91C_BASE_AIC->AIC_EOICR = 0;                          // End of handler                                           

    } else if (except_id == OS_CPU_ARM_EXCEPT_FIQ) {
        pfnct = (CPU_FNCT_VOID)AT91C_BASE_AIC->AIC_FVR;         // Read the interrupt vector from the VIC                  

        while (pfnct != (CPU_FNCT_VOID)0) {                     // Make sure we don't have a NULL pointer                   

          (*pfnct)();                                           // Execute the ISR for the interrupting device             
            AT91C_BASE_AIC->AIC_EOICR = 0;                      // End of handler                                          
            pfnct = (CPU_FNCT_VOID)(AT91C_BASE_AIC->AIC_FVR);   // Read FIQ handler from the AIC                          
        }

        AT91C_BASE_AIC->AIC_EOICR = 0;                          // End of handler                                          

    }
    else {
                                                                // Infinite loop on other exceptions.                      
                                                                // Should be replaced by other behavior (reboot, etc.)      
        while (1) {
            ;
        }
        
    }
    
     OS_CPU_SR_INT_En();
}
*/
/*----------------------------------------------------------------------------*/
void  my_irq_handler()
{
    CPU_FNCT_VOID   pfnct;
    
        pfnct = (CPU_FNCT_VOID)AT91C_BASE_AIC->AIC_IVR;        

        while (pfnct != (CPU_FNCT_VOID)0) {                     

          (*pfnct)();                                           
            AT91C_BASE_AIC->AIC_EOICR = 0;                      
            pfnct = (CPU_FNCT_VOID)(AT91C_BASE_AIC->AIC_IVR);   
        }

        AT91C_BASE_AIC->AIC_EOICR = 0; 
        CPU_SR_INT_En();
 
}

/*-----------------------------------------------------------------------------*/
void  OS_CPU_InitExceptVect (void)
{
    (*(unsigned int *)OS_CPU_ARM_EXCEPT_UNDEF_INSTR_VECT_ADDR)       =         OS_CPU_ARM_INSTR_JUMP_TO_HANDLER;
    (*(unsigned int *)OS_CPU_ARM_EXCEPT_UNDEF_INSTR_HANDLER_ADDR)    = (unsigned int)ARM_ExceptUndefInstrHndlr;

    (*(unsigned int *)OS_CPU_ARM_EXCEPT_SWI_VECT_ADDR)               =         OS_CPU_ARM_INSTR_JUMP_TO_HANDLER;
    (*(unsigned int *)OS_CPU_ARM_EXCEPT_SWI_HANDLER_ADDR)            = (unsigned int)ARM_ExceptSwiHndlr;

    (*(unsigned int *)OS_CPU_ARM_EXCEPT_PREFETCH_ABORT_VECT_ADDR)    =         OS_CPU_ARM_INSTR_JUMP_TO_HANDLER;
    (*(unsigned int *)OS_CPU_ARM_EXCEPT_PREFETCH_ABORT_HANDLER_ADDR) = (unsigned int)ARM_ExceptPrefetchAbortHndlr;

    (*(unsigned int *)OS_CPU_ARM_EXCEPT_DATA_ABORT_VECT_ADDR)        =         OS_CPU_ARM_INSTR_JUMP_TO_HANDLER;
    (*(unsigned int *)OS_CPU_ARM_EXCEPT_DATA_ABORT_HANDLER_ADDR)     = (unsigned int)ARM_ExceptDataAbortHndlr;

    (*(unsigned int *)OS_CPU_ARM_EXCEPT_ADDR_ABORT_VECT_ADDR)        =         OS_CPU_ARM_INSTR_JUMP_TO_HANDLER;
    (*(unsigned int *)OS_CPU_ARM_EXCEPT_ADDR_ABORT_HANDLER_ADDR)     = (unsigned int)ARM_ExceptAddrAbortHndlr;

    (*(unsigned int *)OS_CPU_ARM_EXCEPT_IRQ_VECT_ADDR)               =         OS_CPU_ARM_INSTR_JUMP_TO_HANDLER;
    (*(unsigned int *)OS_CPU_ARM_EXCEPT_IRQ_HANDLER_ADDR)            = (unsigned int)ARM_ExceptIrqHndlr;

    (*(unsigned int *)OS_CPU_ARM_EXCEPT_FIQ_VECT_ADDR)               =         OS_CPU_ARM_INSTR_JUMP_TO_HANDLER;
    (*(unsigned int *)OS_CPU_ARM_EXCEPT_FIQ_HANDLER_ADDR)            = (unsigned int)ARM_ExceptFiqHndlr;
}
/*----------------------------------------------------------------------------*/