test10.v

This is a simple MIPS processor datapath written in VERILOG hardware language. You can see the signa

//jmanous@csd

module test10;


wire [5:0] op, funct;

wire 	     zero;

reg       clk;

reg       pcld;reg [1:0] ALUop;
//upoloipa
reg       IorD, memRd, memWr, irld, mdrld, regDst, regWr;
reg       mem2reg, Bld, Ald, ALUsrcA, cmpsel, ALUld;
reg [1:0] ALUsrcB, pcsel;

// instanciate

datapath10 dat0 (clk, pcld, IorD, memRd, memWr, irld, mdrld, op, funct, regDst, regWr, mem2reg, Bld, Ald, ALUsrcA, ALUsrcB, ALUop, zero, cmpsel, ALUld, pcsel);

`define clk_period 10                  // periodos (se ns)

initial clk = 1;                       // arxikopoihsh tou shmatos sto 1
always clk = #(`clk_period / 2) ~clk;  // dhmiourgia palmwn


//initial

initial begin  

  $shm_open("Test.shm");
  $shm_probe(test10, "AS");
  
  pcld = 0;
  IorD = 0;

  ALUop = 0;
  memRd = 0;
  memWr = 0;
  irld = 0;
  mdrld = 0;
  regDst = 0;
  regWr = 0;
  mem2reg = 0;
  Bld = 0;
  Ald = 0;
  ALUsrcA = 0;
  cmpsel = 0;
  ALUld = 0;

  $readmemh("memory.hex", dat0.mem.data);

  dat0.pcreg.q = 32'h4;


  @(posedge clk);
  #(`hold);              // Perimene ws thn epomenh akmh, kai ligo akoma
  IorD = 0;              // Dieythynsh ths mnhmhs apo PC
  memRd = 1;               // H mnhmh diabazei
  memWr = 0;
  irld = 1;              // To apotelesma ths mnhmhs tha graftei ston ir

  @(posedge clk);
  #(`hold);              // Perimene ws thn epomenh akmh, kai ligo akoma
  irld = 0;              // O ir den tha ksanafortwsei dedomena 
  memRd = 0;               // H mnhmh den diabazei se ayton ton kyklo
  Ald = 1;               // H RegFile diabazei tous kataxwrhtes: fortw-
  Bld = 1;               // noume ta apotelesmata stous A kai B
  
  @(posedge clk);
  #(`hold);              // Perimene ws thn epomenh akmh, kai ligo akoma
  Ald = 0;               // Den ksanagrafontai oi kataxwrhtes
  Bld = 0;
  ALUsrcA = 1;
  ALUsrcB = 2;
  ALUop = 0;
  cmpsel = 1;
  ALUld = 1;

  @(posedge clk);
  #(`hold);
  ALUld = 0;
  regDst = 0;
  mem2reg = 0;
  regWr = 1;
  ALUsrcA = 0;
  ALUsrcB = 1;
  pcsel = 0;
  pcld = 1;

  @(posedge clk);
  #(`hold);
  regWr = 0;
  pcld = 0;
  memRd = 1;
  irld = 1;

  @(posedge clk);
  #(`hold);
  memRd = 0;
  irld = 0;
  Ald = 1;
  Bld = 1;
  
  @(posedge clk);
  #(`hold);
  Ald = 0;
  Bld = 0;
  ALUsrcA = 1;
  ALUsrcB = 2;
  ALUld = 1;

  @(posedge clk);
  #(`hold);
  ALUld = 0;
  memWr = 1;
  IorD = 1;
  ALUsrcA = 0;
  ALUsrcB = 1;
  pcld = 1;  

  @(posedge clk);
  memWr = 0;
  IorD = 0;
  pcld = 0;

  $shm_close();   // Termatimos bashs Signalscan
  $stop;          // Termatismos Verilog-XL

end 

endmodule