datapath10.v

This is a simple MIPS processor datapath written in VERILOG hardware language. You can see the signa

module datapath (pcld,lorD,memRd,memWr,irld.mdrld,op,fucnt,regDest,regWr,mem2reg,Bld,Ald,ALUsrcA,ALUsrcB,ALUop,zero,cmpsel,ALUld,pcsel);

input pcld,IorD,memRd,memWr,irld.mdrld;
input regDest,regWr,mem2reg,Bld,Ald,ALUsrcA,ALUsrcB;
input cmpsel,ALUld,clk;
input [1:0] pcsel,ALUop;
output [5:0] op,fucnt;
output zero;
//const wires//
wire [31:0] const4;

//General purpose wires//
wire [31:0] nxtpc,pc,ma,md,ALUout;
wire [31:0] A,B,ir,mdr,immx,immx4;
wire [31:0] rWD,regA,regB,ALUinA,ALUinB;
wire [31:0] jmpAddr,ALUarith;
wire [4:0] rWa;


//Wires for  instruction split//
wire [25:0] Imm26 = ir[31:6];
wire [4:0] rs = ir[6:10];
wire [4:0] rt = ir[11:15];
wire [4:0] rd = ir[16:20];
wire [15:0] Imm16 = ir[16:31];

/*All assignments*/
assign jmpAddr = {pc[31:28],imm26,2'b00};
assign const4 = 32'h4;
assign op = ir[5:0];
assign funct = ir[26:31];
//sign extension to Imm16 wire.
assign immx = {Imm16[15],Imm16[15:0]};
//shift left twice
assign immx4 = {immx[29:0],2'b00};

//Registers//
RegLd #32 pcreg (pc, nxtpc, pcld, clk);
RegLd #32 irrgeg (ir, md, irld, clk);
RegLd #32 mdrrgeg (mdr, md, mdrld, clk);
RegLd #32 Aload (A, regA, Ald, clk);
RegLd #32 Aload (B, regB, Bld, clk);

//Mux with 2 inputs//
Mux2 #32 muxaddr (ma, pc, ALUout, IorD);
Mux2 #32 muxDst (rWa, rt, rd, regDst); //Write adress choice//
Mux2 #32 muxDwd (rWD, ALUout, mdr, mem2reg); //Write data mux//
Mux2 #32 ALUamux (ALUinA, pc, A, ALUsrcA); //1rst input data choice//

//Mux with 4 inputs//
Mux4 #32 ALUbmux (ALUinB, B, const4, immx, immx4, ALUsrcB);

//Our memory//
Memory mem (memRd, memWr, ma, B, md);

//Our register file//
RegFile rf (rs, rt, rWA, regWr, rWD, regA, regB);