cstartup_eb42.c

This an example of how to install and use interrupts on AT91M4800A-embedded systems when building an

//*----------------------------------------------------------------------------
//*         ATMEL Microcontroller Software Support  -  ROUSSET  -
//*----------------------------------------------------------------------------
//* The software is delivered "AS IS" without warranty or condition of any
//* kind, either express, implied or statutory. This includes without
//* limitation any warranty or condition with respect to merchantability or
//* fitness for any particular purpose, or against the infringements of
//* intellectual property rights of others.
//*----------------------------------------------------------------------------
//* File Name           : Cstartup_EB42.c
//* Object              : Low level initializations written in C for Green Hills
//*                       tools
//* Creation            : JPP 11/Nov/02
//*----------------------------------------------------------------------------

// Include Standard AT91M42800A 
#include "include/AT91M42800A.h"
#include "include/lib_AT91M42800A.h"

// Include the board file description containing the EBI value
#include "eb42.h"

// The following functions must be write in ARM mode this function called directly
// by exception vector
extern void AT91F_Spurious_handler(void);
extern void AT91F_Default_IRQ_handler(void);
extern void AT91F_Default_FIQ_handler(void);

// Vector table definition check this table in ARM file init_reset_eb42.arm
extern unsigned int VectorTable[];
extern unsigned int __ghs_eofn_VectorTable[];
 
// Green Hills link file, define the address for mode Flash or RAM
extern unsigned int __iramstart[];

#pragma ghs section text=".reset" 
//*----------------------------------------------------------------------------
//* \fn    AT91F_LowLevelInit
//* \brief This function performs very low level HW initialization
//*        this function can be use a Stack, depending the compilation 
//*        optimization mode
//* Input Parameters
//* <Vector>  vector table Address determinate in Relative addressing
//* <InternalRam> Internal Address determinate in Relative addressing
//* Output Parameters 
//* <EBI address>
//*----------------------------------------------------------------------------
AT91_REG * AT91F_LowLevelInit( unsigned int * Vector, unsigned int * InternalRam)
{
 int            i;

 AT91PS_EBI     pEbi;
 AT91PS_AIC     pAic;
 AT91PS_PMC     pPMC;
 AT91PS_ST	pST;

        //-----------------------------------------------------------------------------
        // Speed up the Boot sequence
        //---------------------------
        // After reset, the number of wait states on chip select 0 is 8. All AT91 
        // Evaluation Boards fits fast flash memories, so that the number of wait 
        // states can be optimized to fast up the boot sequence.
        //-----------------------------------------------------------------------------
        // set sandart Wait State
        pEbi = AT91C_BASE_EBI ;
        pEbi->EBI_CSR[0] = EBI_CSR_0 ;  

	//---------------------------------------------------------------------------
	//               - Power Management Controller Configuration -              -
	//---------------------------------------------------------------------------
	// At reset, the AT91M42800 runs from the Slow Clock Oscillator @ 32.768Khz.
	// The PLLB is used to run @ 32,768Mhz --> 32,768Khz*(999 + 1)
	//
	// Note:	The lowest working frequency limit for the PLLB is 20 MHz
	//		The highest working frequency limit for the PLLA is 20 MHz
	//		For this reason, according to these limit, the user can select
	//		correctly the PLL choice especially since the PLLS field can be
	//		writing only once, all other writing in this field will be 
	//		ignored.
	//
	//- Disable External Watchdog assertion      -
	//---------------------------------------------------------------------------
	pST = AT91C_BASE_ST;
	pST->ST_WDMR = 0 ;

	//- Set up the Clock frequency if run at 32,768Khz to 32,768 Mhz with PLLB
	//------------------------------------------------------------------------
	pPMC = AT91C_BASE_PMC;

	if ( (pPMC->PMC_CGMR & AT91C_PMC_CSS) == 0) 
	{
	// PLLCOUNT = 197 (6ms, 0xC5), MUL=999 to multiply the oscillator source frequency by using the PLLB
	pPMC->PMC_CGMR = (197 << 24) | (999 << 8) | ( AT91C_PMC_MCKOSS_SLCK |AT91C_PMC_PLLS|AT91C_PMC_PRES_NONE);

	//- Reading the PMC Status Register to detect when the PLLB is stabilized
	//-----------------------------------------------------------------------
	 while ( (pPMC->PMC_SR & AT91C_PMC_LOCK) != AT91C_PMC_LOCK ) {} ;

	//- Switch from Slow Clock (32,768Khz) to PLLB output source (@32,768Mhz)
	//--------------------------------------------------------------------------
	pPMC->PMC_CGMR = (197 << 24) | (999 << 8) | AT91C_PMC_CSS| ( AT91C_PMC_PLLS | AT91C_PMC_MCKOSS_SLCK |AT91C_PMC_PRES_NONE);
	}
	//---------------------------------------------------------
	//- Now the Master clock is the output of PLLA @ 32,768MHz -
	//---------------------------------------------------------
        //-----------------------------------------------------------------------------
        //  Set up EBI value
        //--------------------
        // After reset, All EBI register are setted at the default value 
        // The new value will be effective only after the remap command
        //-----------------------------------------------------------------------------
        // Load System pEbi Base address and CSR0 Init Value
        pEbi->EBI_CSR[1] = EBI_CSR_1 ;
        pEbi->EBI_CSR[2] = EBI_CSR_2 ;
        pEbi->EBI_CSR[3] = EBI_CSR_3 ;
        pEbi->EBI_CSR[4] = EBI_CSR_4 ;
        pEbi->EBI_CSR[5] = EBI_CSR_5 ;
        pEbi->EBI_CSR[6] = EBI_CSR_6 ;
        pEbi->EBI_CSR[7] = EBI_CSR_7 ;
        // 6 memory regions, standard read
        pEbi->EBI_MCR = 6 ;
        //-----------------------------------------------------------------------------
        // Reset the Interrupt Controller
        //-------------------------------
        // Normally, the code is executed only if a reset has been actually performed.
        // So, the AIC initialization resumes at setting up the default vectors.
        //-----------------------------------------------------------------------------
        // Load System pAic Base address 
        pAic = AT91C_BASE_AIC; 
        
        // Mask All interrupt
        pAic->AIC_IDCR = 0xFFFFFFFF;
        
        // Perform 8 End Of Interrupt Command to make sure AIC will not Lock out nIRQ 
        for (i=0;i < 8; i++)
        {
                AT91F_AIC_AcknowledgeIt(AT91C_BASE_AIC);
        }

        // Set up the default interrupts handler vectors
        pAic->AIC_SVR[0] = (int) AT91F_Default_FIQ_handler ;
        for (i=1;i < 31; i++)
        {
                pAic->AIC_SVR[i] = (int) AT91F_Default_IRQ_handler ;
        }
        pAic->AIC_SPU  = (int) AT91F_Spurious_handler ;
        
        // Setup Exception Vectors in Internal RAM before Remap
        //-----------------------------------------------------
        // That's important to perform this operation before Remap in order to guarantee
        // that the core has valid vectors at any time during the remap operation.
        // Note: There are only 5 offsets as the vectoring is used.
        // Before Remap the internal RAM it's 0x300000
        // After  Remap the internal RAM it's 0x000000
        // Remap it's already executed it's no possible to write to 0x300000.
        //-----------------------------------------------------------------------------
        //  Copy the ARM exception vectors and indirect table

        for  (i=0;i < __ghs_eofn_VectorTable-VectorTable; i++ )
        {
           *InternalRam++=*Vector++;
        }

        return ( &pEbi->EBI_RCR); 
}