vectors.s

IR Decoding source code

/* M68HC11 Interrupt vectors table
   Copyright (C) 1999 Free Software Foundation, Inc.
   Written by Stephane Carrez ([e-mail])	

This file is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the
Free Software Foundation; either version 2, or (at your option) any
later version.

In addition to the permissions in the GNU General Public License, the
Free Software Foundation gives you unlimited permission to link the
compiled version of this file with other programs, and to distribute
those programs without any restriction coming from the use of this
file.  (The General Public License restrictions do apply in other
respects; for example, they cover modification of the file, and
distribution when not linked into another program.)

This file is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
General Public License for more details.

You should have received a copy of the GNU General Public License
along with this program; see the file COPYING.  If not, write to
the Free Software Foundation, 59 Temple Place - Suite 330,
Boston, MA 02111-1307, USA.  */

        .include         "../include/symbols.f1w.h"

        
	.sect .text
        .globl _start

;; Default interrupt handler.
	.sect .text
def:
	rti
begin:
	ldx     #REGBS
; timer prescaler (10 for 16Mhz, 01 for 8Mhz)
        ldaa    #0b00000010
        staa    TMSK2,X

; program memory is 32k (write 5 to CSCTL)
	ldaa  #5
	staa  0x5d,x

; ram is 32k (write 1 to CSGSIZ)
	ldaa  #1
	staa  0x5f,x

        bra     _start
;; 
;; Interrupt vectors are in a specific section that is
;; mapped at 0xffc0. For the example program, the reset handler
;; points to the generic crt0 entry point.
;;
	.sect .vectors
	.globl vectors
        .globl begin
        .globl ic3isr
vectors:
	.word def		; ffc0
	.word def		; ffc2
	.word def		; ffc4
	.word def		; ffc6
	.word def		; ffc8
	.word def		; ffca
	.word def		; ffcc
	.word def		; ffce
	.word def		; ffd0
	.word def		; ffd2
	.word def		; ffd4

	;; SCI
	.word def		; ffd6

	;; SPI
	.word def		; ffd8
	.word def		; ffda (PAII)
	.word def		; ffdc (PAOVI)
	.word def		; ffde (TOI)

	;; Timer Output Compare
oc1vec: .word def		; ffe0
oc2vec: .word def		; ffe2
oc3vec: .word def		; ffe4
oc4vec:	.word def		; ffe6
	.word def		; ffe8

	;; Timer Input compare
ic3vec: .word ic3isr		; ffea
	.word def		; ffec
	.word def		; ffee

	;;  Misc
rtivec: .word def               ; fff0 (RTII)
irqvec: .word def		; fff2 (IRQ)
xirvec: .word def		; fff4 (XIRQ)
swivec: .word def		; fff6 (SWI)
illvec: .word def		; fff8 (ILL)
copvec: .word def		; fffa (COP Failure)
clkvec: .word def		; fffc (COP Clock monitor)
rstvec: .word begin		; fffe (reset)