str91x.s

This is an Real-Time Library (RL-ARM) Flash File System file manipulation example.

;//     <o1.9>          RST_USB: USB peripheral reset
;//       <0=> In reset <1=> Not in reset
;//       <i> Default: In reset
;//     <o1.8>          RST_DMA: DMA peripheral reset
;//       <0=> In reset <1=> Not in reset
;//       <i> Default: In reset
;//     <o1.6>          RST_EMI: EMI peripheral reset
;//       <0=> In reset <1=> Not in reset
;//       <i> Default: Not in reset
;//     <o1.5>          RST_VIC: VIC peripheral reset
;//       <0=> In reset <1=> Not in reset
;//       <i> Default: In reset
;//     <o1.4> RST_SRAM_ARBITER: SRAM arbiter reset
;//       <0=> In reset <1=> Not in reset
;//       <i> Default: Not in reset
;//     <o1.1>        RST_PQFBC: PQFBC reset
;//       <0=> In reset <1=> Not in reset
;//       <i> Default: Not in reset
;//     <o1.0>          RST_FMI: FMI reset
;//       <0=> In reset <1=> Not in reset
;//       <i> Default: Not in reset
;//   </h>
;//   <h> Peripheral Reset Register 1 Configuration (SCU_PRR1)
;//     <o2.24>         RST_RTC: RTC reset
;//       <0=> In reset <1=> Not in reset
;//       <i> Default: In reset
;//     <o2.23>       RST_GPIO9: GPIO9 Port reset
;//       <0=> In reset <1=> Not in reset
;//       <i> Default: In reset
;//     <o2.22>       RST_GPIO8: GPIO8 Port reset
;//       <0=> In reset <1=> Not in reset
;//       <i> Default: In reset
;//     <o2.21>       RST_GPIO7: GPIO7 Port reset
;//       <0=> In reset <1=> Not in reset
;//       <i> Default: In reset
;//     <o2.20>       RST_GPIO6: GPIO6 Port reset
;//       <0=> In reset <1=> Not in reset
;//       <i> Default: In reset
;//     <o2.19>       RST_GPIO5: GPIO5 Port reset
;//       <0=> In reset <1=> Not in reset
;//       <i> Default: In reset
;//     <o2.18>       RST_GPIO4: GPIO4 Port reset
;//       <0=> In reset <1=> Not in reset
;//       <i> Default: In reset
;//     <o2.17>       RST_GPIO3: GPIO3 Port reset
;//       <0=> In reset <1=> Not in reset
;//       <i> Default: In reset
;//     <o2.16>       RST_GPIO2: GPIO2 Port reset
;//       <0=> In reset <1=> Not in reset
;//       <i> Default: In reset
;//     <o2.15>       RST_GPIO1: GPIO1 Port reset
;//       <0=> In reset <1=> Not in reset
;//       <i> Default: In reset
;//     <o2.14>       RST_GPIO0: GPIO0 Port reset
;//       <0=> In reset <1=> Not in reset
;//       <i> Default: In reset
;//     <o2.13>         RST_WIU: WIU peripheral reset
;//       <0=> In reset <1=> Not in reset
;//       <i> Default: In reset
;//     <o2.12>         RST_WDG: WDG peripheral reset
;//       <0=> In reset <1=> Not in reset
;//       <i> Default: In reset
;//     <o2.11>         RST_ADC: ADC reset
;//       <0=> In reset <1=> Not in reset
;//       <i> Default: In reset
;//     <o2.10>         RST_CAN: CAN peripheral reset
;//       <0=> In reset <1=> Not in reset
;//       <i> Default: In reset
;//     <o2.9>         RST_SSP1: SSP1 peripheral reset
;//       <0=> In reset <1=> Not in reset
;//       <i> Default: In reset
;//     <o2.8>         RST_SSP0: SSP0 peripheral reset
;//       <0=> In reset <1=> Not in reset
;//       <i> Default: In reset
;//     <o2.7>         RST_I2C1: I2C1 peripheral reset
;//       <0=> In reset <1=> Not in reset
;//       <i> Default: In reset
;//     <o2.6>         RST_I2C0: I2C0 peripheral reset
;//       <0=> In reset <1=> Not in reset
;//       <i> Default: In reset
;//     <o2.5>        RST_UART2: UART2 peripheral reset
;//       <0=> In reset <1=> Not in reset
;//       <i> Default: In reset
;//     <o2.4>        RST_UART1: UART1 peripheral reset
;//       <0=> In reset <1=> Not in reset
;//       <i> Default: In reset
;//     <o2.3>        RST_UART0: UART0 peripheral reset
;//       <0=> In reset <1=> Not in reset
;//       <i> Default: In reset
;//     <o2.2>           RST_MC: Motor Control peripheral reset
;//       <0=> In reset <1=> Not in reset
;//       <i> Default: In reset
;//     <o2.1>        RST_TIM23: Timers 2 and 3 reset
;//       <0=> In reset <1=> Not in reset
;//       <i> Default: In reset
;//     <o2.0>        RST_TIM01: Timers 0 and 1 reset
;//       <0=> In reset <1=> Not in reset
;//       <i> Default: In reset
;//   </h>
;// </e1> End of Clock Configuration
P_RESET_SETUP   EQU     1
SCU_PRR0_Val    EQU     0x00001073
SCU_PRR1_Val    EQU     0x00E80110


; APB Bridge 1 & 2 definitions (Peripherals)
APB0_BUF_BASE   EQU     0x48001802      ; APB Bridge 0 Buffered Base Address
APB0_NBUF_BASE  EQU     0x58000000      ; APB Bridge 0 Non-buffered Base Address
APB1_BUF_BASE   EQU     0x4C000000      ; APB Bridge 1 Buffered Base Address
APB1_NBUF_BASE  EQU     0x5C000000      ; APB Bridge 1 Non-buffered Base Address


;// <e> Setup Library Exception Handlers
LEH_SETUP       EQU     0
;// </e>


                PRESERVE8


; Area Definition and Entry Point
;  Startup Code must be linked first at Address at which it expects to run.

                AREA    Reset, CODE, READONLY
                ARM

; Exception Vectors
;  Mapped to Address 0.
;  Absolute addressing mode must be used.
;  Dummy Handlers are implemented as infinite loops which can be modified.


Vectors         LDR     PC, Reset_Addr         
                LDR     PC, Undef_Addr
                LDR     PC, SWI_Addr
                LDR     PC, PAbt_Addr
                LDR     PC, DAbt_Addr
                NOP                         ; Reserved Vector 
;                LDR     PC, IRQ_Addr
                LDR     PC, [PC, #-0x0FF0]
                LDR     PC, FIQ_Addr

                IF      LEH_SETUP <> 0
                EXTERN  UndefHandler
                EXTERN  SWIHandler
                EXTERN  PAbtHandler
                EXTERN  DAbtHandler
                EXTERN  IRQHandler
                EXTERN  FIQHandler
                ENDIF
                
Reset_Addr      DCD     Reset_Handler
Undef_Addr      DCD     UndefHandler
SWI_Addr        DCD     SWIHandler
PAbt_Addr       DCD     PAbtHandler
DAbt_Addr       DCD     DAbtHandler
                DCD     0                   ; Reserved Address 
IRQ_Addr        DCD     IRQHandler
FIQ_Addr        DCD     FIQHandler

                
                IF      LEH_SETUP = 0
                
UndefHandler    B       UndefHandler
SWIHandler      B       SWIHandler
PAbtHandler     B       PAbtHandler
DAbtHandler     B       DAbtHandler
IRQHandler      B       IRQHandler
FIQHandler      B       FIQHandler

                ENDIF


; Reset Handler

                EXPORT  Reset_Handler
Reset_Handler   

                NOP     ; Wait for OSC stabilization
                NOP
                NOP
                NOP
                NOP
                NOP
                NOP
                NOP


; Setup System Configuration (and SRAM Size)
                IF      SCR0_SETUP == 1

                LDR     R0, =SCU_BASE
                LDR     R1, =SCU_SCR0_Val
                STR     R1, [R0, #SCU_SCR0_OFS]

                ENDIF


; Setup Flash Memory Interface (FMI)
                IF      FMI_SETUP == 1

                LDR     R0, =FMI_BASE
                LDR     R1, =FMI_BBSR_Val
                STR     R1, [R0, #FMI_BBSR_OFS]
                LDR     R1, =FMI_NBBSR_Val
                STR     R1, [R0, #FMI_NBBSR_OFS]
                LDR     R1, =(FMI_BBADR_Val:SHR:2)
                STR     R1, [R0, #FMI_BBADR_OFS]
                LDR     R1, =(FMI_NBBADR_Val:SHR:2)
                STR     R1, [R0, #FMI_NBBADR_OFS]
                LDR     R2, =FMI_CR_Val
                STR     R2, [R0, #FMI_CR_OFS]

                ; Write "Write flash configuration" command (60h)
                MOV     R0, R1, LSL #2
                MOV     R1, #0x60
                STRH    R1, [R0, #0]

                ; Write "Write flash configuration confirm" command (03h)
                LDR     R2, =(FLASH_CFG_Val:SHL:2)
                ADD     R0, R0, R2
                MOV     R1, #0x03
                STRH    R1, [R0, #0]

                ENDIF


; Setup Clock
                IF      CLOCK_SETUP == 1

                LDR     R0, =SCU_BASE
                LDR     R1, =0x00020002
                STR     R1, [R0, #SCU_CLKCNTR_OFS]    ; Select OSC as clk src

                NOP     ; Wait for OSC stabilization
                NOP
                NOP
                NOP
                NOP
                NOP
                NOP
                NOP
                NOP
                NOP
                NOP
                NOP

                LDR     R1, =0x0003C019               ; PLL to default
                STR     R1, [R0, #SCU_PLLCONF_OFS]
                LDR     R1, =SCU_PLLCONF_Val          ; PLL to requested value
                STR     R1, [R0, #SCU_PLLCONF_OFS]

                ; Wait until PLL is stabilized (if PLL enabled)
                IF      (SCU_PLLCONF_Val:AND:0x80000) != 0
PLL_Loop        LDR     R2, [R0, #SCU_SYSSTAT_OFS]
                ANDS    R2, R2, #SYSSTAT_LOCK
                BEQ     PLL_Loop
                ENDIF

                LDR     R1, =SCU_CLKCNTR_Val          ; Setup clock control
                STR     R1, [R0, #SCU_CLKCNTR_OFS]

                LDR     R1, =SCU_PCGR0_Val            ; Enable clock gating
                STR     R1, [R0, #SCU_PCGR0_OFS]
                LDR     R1, =SCU_PCGR1_Val
                STR     R1, [R0, #SCU_PCGR1_OFS]

                ENDIF


; Setup Peripheral Reset
                IF      P_RESET_SETUP != 0
                LDR     R1, =SCU_PRR0_Val
                STR     R1, [R0, #SCU_PRR0_OFS]
                LDR     R1, =SCU_PRR1_Val
                STR     R1, [R0, #SCU_PRR1_OFS]
                ENDIF


; Setup Stack for each mode

                LDR     R0, =Stack_Top

;  Enter Undefined Instruction Mode and set its Stack Pointer
                MSR     CPSR_c, #Mode_UND:OR:I_Bit:OR:F_Bit
                MOV     SP, R0
                SUB     R0, R0, #UND_Stack_Size

;  Enter Abort Mode and set its Stack Pointer
                MSR     CPSR_c, #Mode_ABT:OR:I_Bit:OR:F_Bit
                MOV     SP, R0
                SUB     R0, R0, #ABT_Stack_Size

;  Enter FIQ Mode and set its Stack Pointer
                MSR     CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F_Bit
                MOV     SP, R0
                SUB     R0, R0, #FIQ_Stack_Size

;  Enter IRQ Mode and set its Stack Pointer
                MSR     CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit
                MOV     SP, R0
                SUB     R0, R0, #IRQ_Stack_Size

;  Enter Supervisor Mode and set its Stack Pointer
                MSR     CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit
                MOV     SP, R0
                SUB     R0, R0, #SVC_Stack_Size

;  Enter User Mode and set its Stack Pointer
                MSR     CPSR_c, #Mode_USR
                IF      :DEF:__MICROLIB

                EXPORT __initial_sp

                ELSE

                MOV     SP, R0
                SUB     SL, SP, #USR_Stack_Size

                ENDIF


; Enter the C code

                IMPORT  __main
                LDR     R0, =__main
                BX      R0


                IF      :DEF:__MICROLIB

                EXPORT  __heap_base
                EXPORT  __heap_limit

                ELSE
; User Initial Stack & Heap
                AREA    |.text|, CODE, READONLY

                IMPORT  __use_two_region_memory
                EXPORT  __user_initial_stackheap
__user_initial_stackheap

                LDR     R0, =  Heap_Mem
                LDR     R1, =(Stack_Mem + USR_Stack_Size)
                LDR     R2, = (Heap_Mem +      Heap_Size)
                LDR     R3, = Stack_Mem
                BX      LR
                ENDIF


                END