📄 sp_serialflashv1.lst
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<
< // Define for P_ADC_Ctrl
< //----------------------------------------------
< .if BODY_TYPE == SPCE061A
< .DEFINE C_AD_Enable 0x0001; //b0=1: enable A/D converter
< .DEFINE C_AD_Disable 0x0000; //b0=0: disable A/D converter
< .DEFINE C_AD_Line_In 0x0002; //b1=1: microphone disable
< .DEFINE C_AD_MIC_In 0x0000; //b1=0: microphone enable
< .DEFINE C_AGC_Enable 0x0004; //b2=1: enable AGC function
< .DEFINE C_AGC_Disable 0x0000; //b2=0: disable AGC function
< .DEFINE C_AD_Sample 0x0004; //b3=1: sample the analog signal(manual mode)
< .DEFINE C_AD_Hold 0x0000; //b3=0: hold(manual mode)
< .DEFINE C_Auto_Mode 0x0010; //b4=1: A/D auto mode
< .DEFINE C_Manual_Mode 0x0000; //b4=0: A/D manual mode
< //b5: ADINI?
< .DEFINE C_DAC_Current_2mA 0x0040; //b6=1: DAC current = 2mA @ vdd=3V(new option)
< .DEFINE C_DAC_Current_3mA 0x0000; //b6=0: DAC current = 3mA @ vdd=3V(Default)
< .DEFINE C_AD_Vref_VDD 0x0080; //b7=1: Vref is VDD
< .DEFINE C_AD_Vref_VRTPAD 0x0000; //b7=0: Vref is from pin "VRTPAD"
< .DEFINE C_AD_COMP 0x4000; //b14=1: output voltage of DAC0<Analog input signal
< //b14=0: output voltage of DAC0>Analog input signal
< .DEFINE C_AD_RDY 0x8000; //b15=1: A/D digital data ready; 0: not ready
< .endif
<
< .if BODY_TYPE == SPCE500A
< .DEFINE C_AD 0x0001 //
< .DEFINE C_DA 0x0000 //
< .DEFINE C_MIC 0x0000 //
< .DEFINE C_LINE 0x0002 //
< .endif
< //----------------------------------------------
<
<
< // Define for P_DAC_Ctrl
< //----------------------------------------------
< .if BODY_TYPE == SPCE061A
< .DEFINE C_DAC1_Direct 0x0000; // b8 b7: DAC1 latch
< .DEFINE C_DAC1_LatchA 0x0080; // Latch data to DAC1 by TimerA
< .DEFINE C_DAC1_LatchB 0x0100; // Latch data to DAC1 by TimerB
< .DEFINE C_DAC1_LatchAB 0x0180; // Latch data to DAC1 by TimerA or TimerB
<
< .DEFINE C_DAC2_Direct 0x0000; // b6 b5: DAC2 latch
< .DEFINE C_DAC2_LatchA 0x0020; // Latch data to DAC2 by TimerA
< .DEFINE C_DAC2_LatchB 0x0040; // Latch data to DAC2 by TimerB
< .DEFINE C_DAC2_LatchAB 0x0060; // Latch data to DAC2 by TimerA or TimerB
<
< .DEFINE C_ADC_Direct 0x0000; // b4 b3: ADC latch
< .DEFINE C_ADC_LatchA 0x0008; // Latch data to ADC by TimerA
< .DEFINE C_ADC_LatchB 0x0010; // Latch data to ADC by TimerB
< .DEFINE C_ADC_LatchAB 0x0018; // Latch data to ADC by TimerA or TimerB
< .endif
<
< .if BODY_TYPE == SPCE500A
< .DEFINE C_PushPull 0x0000 // b0, (default)
< .DEFINE C_DoubleEnd 0x0001 // b0
< .DEFINE C_DAC_Mode 0x0000 // b1, (default)
< .DEFINE C_PWM_Mode 0x0002 // b1
<
< .DEFINE C_D1_Direct 0x0000 // DAC1 latch
< .DEFINE C_D1_LatchA 0x0008 //
< .DEFINE C_D1_LatchB 0x0010 //
< .DEFINE C_D1_LatchAB 0x0018 //
<
< .DEFINE C_D2_Direct 0x0000 // DAC2 latch
< .DEFINE C_D2_LatchA 0x0020 //
< .DEFINE C_D2_LatchB 0x0040 //
< .DEFINE C_D2_LatchAB 0x00C0 //
< .endif
< //----------------------------------------------
<
< // Define for P_LVD_Ctrl
< //----------------------------------------------
< .if BODY_TYPE == SPCE061A
< .DEFINE C_LVD24V 0x0000; // LVD = 2.4V; b1b0
< .DEFINE C_LVD28V 0x0001; // LVD = 2.8V
< .DEFINE C_LVD32V 0x0002; // LVD = 3.2V
< .endif
<
< .if BODY_TYPE == SPCE500A
< .DEFINE C_LVD26V 0x0000 // LVD = 2.6V
< .DEFINE C_LVD30V 0x0001 // LVD = 3.0V
< .DEFINE C_LVD36V 0x0002 // LVD = 3.6V
< .DEFINE C_LVD40V 0x0003 // LVD = 4.0V
< .endif
<
< .DEFINE C_LVD_Result 0x8000; // b15 = 1: below the selected LVD level
< //----------------------------------------------
<
<
< // SPCE061 flash operation instruction definition
< //----------------------------------------------
< .if BODY_TYPE == SPCE061A
< .DEFINE C_EnableFlashAccess 0xAAAA;
< .DEFINE C_EraseFlashPage 0x5511;
< .DEFINE C_ProgramFlash 0x5533;
< .endif
< //----------------------------------------------
<
<
<
< //===============================================================
< // Sunplus APIs for SPCE 061A
< //===============================================================
< //////////////////////////////////////////////////
< // Note: This register will map to the P_INT_Ctrl
< // (0x7010), The SACMvxx.lib use this register to
< // combine with user's interrupt setting.
< // In SPCE061, it is not necessary since the
< // P_INT_Mask(0x702D) already does this. It is for
< // compatibility to keep it here.
< //////////////////////////////////////////////////
< //.EXTERNAL R_InterruptStatus
<
< //========================================================================================
< // End of SPCE061A.inc
< //========================================================================================
<
<
<
.DEFINE C_SIOCLOCK 0x0010; // CPUCLOCK/8
0000A03A .CODE
//////////////////////////////////////////////////////////////////
// Function: Send A Byte to Serial Flash
// Syntax: SP_SIOSendAByte(AddressLow,AddressHigh, data)
// c level public
// Used register: r1,r2,r3
//////////////////////////////////////////////////////////////////
.public _SP_SIOSendAByte;
_SP_SIOSendAByte: .PROC
F_SIOSendAByte:
0000A03A 88 DA PUSH BP,BP TO [SP];
0000A03B 08 0B 01 00 BP = SP + 1;
0000A03D 03 92 R1 = [BP+3];
0000A03E 19 D3 1B 70 [P_SIO_Addr_Low]=r1; // input SFLASH low address
0000A040 79 93 r1=r1 lsr 4; // right shift 8
0000A041 79 93 r1=r1 lsr 4;
0000A042 19 D3 1C 70 [P_SIO_Addr_Mid]=r1; // input SFLASH mid address
0000A044 04 92 R1 = [BP+4]; // Port direction
0000A045 47 B2 r1=r1&0x0007; // input SFLASH hi address
0000A046 19 D3 1D 70 [P_SIO_Addr_High]=r1;
0000A048 09 93 D3 00 r1=0x00C3+C_SIOCLOCK;
0000A04A 19 D3 1E 70 [P_SIO_Ctrl]=r1; // clk=CPUclk/8, 24 bit address ;write
0000A04C 19 D3 1F 70 [P_SIO_Start]=r1; // enable write mode
0000A04E 05 92 R1 = [BP+5];
0000A04F 19 D3 1A 70 [P_SIO_Data]=r1; // state to transmit data
L_WaitSIOSendReady:
0000A051 11 93 1F 70 r1=[P_SIO_Start];
0000A053 09 C3 80 00 test r1,0x0080
0000A055 45 4E jnz L_WaitSIOSendReady
0000A056 19 D3 20 70 [P_SIO_Stop]=r1; //disable write mode
0000A058 88 98 POP BP,BP FROM [SP];
0000A059 90 9A retf;
.ENDP;
//////////////////////////////////////////////////////////////////
// Function: Read A Byte to Serial Flash
// Syntax: SP_SIOReadAByte(AddressLow, AddressHigh)
// c level public
// Used register: r1,r2,r3
// Return register: r1
//////////////////////////////////////////////////////////////////
.public _SP_SIOReadAByte;
_SP_SIOReadAByte: .PROC
F_SIOReadAByte:
0000A05A 88 DA PUSH BP,BP TO [SP];
0000A05B 08 0B 01 00 BP = SP + 1;
0000A05D 03 92 R1 = [BP+3];
0000A05E 19 D3 1B 70 [P_SIO_Addr_Low]=r1; // input SFLASH low address
0000A060 79 93 r1=r1 lsr 4;
0000A061 79 93 r1=r1 lsr 4;
0000A062 19 D3 1C 70 [P_SIO_Addr_Mid]=r1; // input SFLASH mid address
0000A064 04 92 R1 = [BP+4]; // Port direction
0000A065 47 B2 r1=r1&0x0007; // input SFLASH hi address
0000A066 19 D3 1D 70 [P_SIO_Addr_High]=r1;
0000A068 09 93 93 00 r1=0x0083+C_SIOCLOCK;
0000A06A 19 D3 1E 70 [P_SIO_Ctrl]=r1; // clk=CPUclk/16, 24 bit address ;read
0000A06C 19 D3 1F 70 [P_SIO_Start]=r1; // enable read mode
0000A06E 12 95 1A 70 r2=[P_SIO_Data]; // Clear SFLASH buffer
L_WaitSIOReadReady1:
0000A070 11 93 1F 70 r1=[P_SIO_Start];
0000A072 09 C3 80 00 test r1,0x0080
0000A074 45 4E jnz L_WaitSIOReadReady1
0000A075 11 93 1A 70 r1=[P_SIO_Data]; // Read exact Data
L_WaitSIOReadReady2: // Wait read stop
0000A077 12 95 1F 70 r2=[P_SIO_Start];
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