📄 uartapi.lst
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< .DEFINE C_AGC_Enable 0x0004; //b2=1: enable AGC function
< .DEFINE C_AGC_Disable 0x0000; //b2=0: disable AGC function
< .DEFINE C_AD_Sample 0x0004; //b3=1: sample the analog signal(manual mode)
< .DEFINE C_AD_Hold 0x0000; //b3=0: hold(manual mode)
< .DEFINE C_Auto_Mode 0x0010; //b4=1: A/D auto mode
< .DEFINE C_Manual_Mode 0x0000; //b4=0: A/D manual mode
< //b5: ADINI?
< .DEFINE C_DAC_Current_2mA 0x0040; //b6=1: DAC current = 2mA @ vdd=3V(new option)
< .DEFINE C_DAC_Current_3mA 0x0000; //b6=0: DAC current = 3mA @ vdd=3V(Default)
< .DEFINE C_AD_Vref_VDD 0x0080; //b7=1: Vref is VDD
< .DEFINE C_AD_Vref_VRTPAD 0x0000; //b7=0: Vref is from pin "VRTPAD"
< .DEFINE C_AD_COMP 0x4000; //b14=1: output voltage of DAC0<Analog input signal
< //b14=0: output voltage of DAC0>Analog input signal
< .DEFINE C_AD_RDY 0x8000; //b15=1: A/D digital data ready; 0: not ready
< .endif
<
< .if BODY_TYPE == SPCE500A
< .DEFINE C_AD 0x0001 //
< .DEFINE C_DA 0x0000 //
< .DEFINE C_MIC 0x0000 //
< .DEFINE C_LINE 0x0002 //
< .endif
< //----------------------------------------------
<
<
< // Define for P_DAC_Ctrl
< //----------------------------------------------
< .if BODY_TYPE == SPCE061A
< .DEFINE C_DAC1_Direct 0x0000; // b8 b7: DAC1 latch
< .DEFINE C_DAC1_LatchA 0x0080; // Latch data to DAC1 by TimerA
< .DEFINE C_DAC1_LatchB 0x0100; // Latch data to DAC1 by TimerB
< .DEFINE C_DAC1_LatchAB 0x0180; // Latch data to DAC1 by TimerA or TimerB
<
< .DEFINE C_DAC2_Direct 0x0000; // b6 b5: DAC2 latch
< .DEFINE C_DAC2_LatchA 0x0020; // Latch data to DAC2 by TimerA
< .DEFINE C_DAC2_LatchB 0x0040; // Latch data to DAC2 by TimerB
< .DEFINE C_DAC2_LatchAB 0x0060; // Latch data to DAC2 by TimerA or TimerB
<
< .DEFINE C_ADC_Direct 0x0000; // b4 b3: ADC latch
< .DEFINE C_ADC_LatchA 0x0008; // Latch data to ADC by TimerA
< .DEFINE C_ADC_LatchB 0x0010; // Latch data to ADC by TimerB
< .DEFINE C_ADC_LatchAB 0x0018; // Latch data to ADC by TimerA or TimerB
< .endif
<
< .if BODY_TYPE == SPCE500A
< .DEFINE C_PushPull 0x0000 // b0, (default)
< .DEFINE C_DoubleEnd 0x0001 // b0
< .DEFINE C_DAC_Mode 0x0000 // b1, (default)
< .DEFINE C_PWM_Mode 0x0002 // b1
<
< .DEFINE C_D1_Direct 0x0000 // DAC1 latch
< .DEFINE C_D1_LatchA 0x0008 //
< .DEFINE C_D1_LatchB 0x0010 //
< .DEFINE C_D1_LatchAB 0x0018 //
<
< .DEFINE C_D2_Direct 0x0000 // DAC2 latch
< .DEFINE C_D2_LatchA 0x0020 //
< .DEFINE C_D2_LatchB 0x0040 //
< .DEFINE C_D2_LatchAB 0x00C0 //
< .endif
< //----------------------------------------------
<
< // Define for P_LVD_Ctrl
< //----------------------------------------------
< .if BODY_TYPE == SPCE061A
< .DEFINE C_LVD24V 0x0000; // LVD = 2.4V; b1b0
< .DEFINE C_LVD28V 0x0001; // LVD = 2.8V
< .DEFINE C_LVD32V 0x0002; // LVD = 3.2V
< .endif
<
< .if BODY_TYPE == SPCE500A
< .DEFINE C_LVD26V 0x0000 // LVD = 2.6V
< .DEFINE C_LVD30V 0x0001 // LVD = 3.0V
< .DEFINE C_LVD36V 0x0002 // LVD = 3.6V
< .DEFINE C_LVD40V 0x0003 // LVD = 4.0V
< .endif
<
< .DEFINE C_LVD_Result 0x8000; // b15 = 1: below the selected LVD level
< //----------------------------------------------
<
<
< // SPCE061 flash operation instruction definition
< //----------------------------------------------
< .if BODY_TYPE == SPCE061A
< .DEFINE C_EnableFlashAccess 0xAAAA;
< .DEFINE C_EraseFlashPage 0x5511;
< .DEFINE C_ProgramFlash 0x5533;
< .endif
< //----------------------------------------------
<
<
<
< //===============================================================
< // Sunplus APIs for SPCE 061A
< //===============================================================
< //////////////////////////////////////////////////
< // Note: This register will map to the P_INT_Ctrl
< // (0x7010), The SACMvxx.lib use this register to
< // combine with user's interrupt setting.
< // In SPCE061, it is not necessary since the
< // P_INT_Mask(0x702D) already does this. It is for
< // compatibility to keep it here.
< //////////////////////////////////////////////////
< //.EXTERNAL R_InterruptStatus
<
< //========================================================================================
< // End of SPCE061A.inc
< //========================================================================================
<
<
<
.INCLUDE UART.inc;
< //========================================================================================
< // Progarm: The assembly inc file for UART on SPCE 500/061 V1.0
< // Arranged by: Arthur Shieh
< // Date: 2002/09/27: first version
< //
< // Note: This inc file defines the ports available for user to use SPCE 500.
< // The UART setting constants is also included for users' convenience.
< //========================================================================================
< //----------------------------------------------------------
< //CPU Type definition
< //----------------------------------------------------------
<
< .define FoscForUart 24 // SPCE500
< //.define FoscForUart 49 // SPCE061
< // Include hardware information
<
<
< //----------------------------------------------------------
< //////////////////////////////////////////////////////////////////
< // Definitions for UART Port
< //////////////////////////////////////////////////////////////////
< .if FoscForUart == 24
< // Baud Rate Setting for Fose at 24.576MHz
< .DEFINE C_UARTBaudRate_1500_H 0x1F
< .DEFINE C_UARTBaudRate_1500_L 0xFF
< .DEFINE C_UARTBaudRate_2400_H 0x14
< .DEFINE C_UARTBaudRate_2400_L 0x00
< .DEFINE C_UARTBaudRate_4800_H 0x0A
< .DEFINE C_UARTBaudRate_4800_L 0x00
< .DEFINE C_UARTBaudRate_9600_H 0x05
< .DEFINE C_UARTBaudRate_9600_L 0x00
< .DEFINE C_UARTBaudRate_19200_H 0x02
< .DEFINE C_UARTBaudRate_19200_L 0x80
< .DEFINE C_UARTBaudRate_38400_H 0x01
< .DEFINE C_UARTBaudRate_38400_L 0x40
< .DEFINE C_UARTBaudRate_48000_H 0x01 // Default
< .DEFINE C_UARTBaudRate_48000_L 0x00
< .DEFINE C_UARTBaudRate_51200_H 0x00
< .DEFINE C_UARTBaudRate_51200_L 0xF0
< .DEFINE C_UARTBaudRate_57600_H 0x00
< .DEFINE C_UARTBaudRate_57600_L 0xD5
< .DEFINE C_UARTBaudRate_102400_H 0x00
< .DEFINE C_UARTBaudRate_102400_L 0x78
< .DEFINE C_UARTBaudRate_115200_H 0x00
< .DEFINE C_UARTBaudRate_115200_L 0x6B
< .endif
<
< .if FoscForUart == 49
< // Baud Rate Setting for Fose at 49.152MHz
< .DEFINE C_UARTBaudRate_1500_H 0x40
< .DEFINE C_UARTBaudRate_1500_L 0x00
< .DEFINE C_UARTBaudRate_2400_H 0x28
< .DEFINE C_UARTBaudRate_2400_L 0x00
< .DEFINE C_UARTBaudRate_4800_H 0x14
< .DEFINE C_UARTBaudRate_4800_L 0x00
< .DEFINE C_UARTBaudRate_9600_H 0x0A
< .DEFINE C_UARTBaudRate_9600_L 0x00
< .DEFINE C_UARTBaudRate_19200_H 0x05
< .DEFINE C_UARTBaudRate_19200_L 0x00
< .DEFINE C_UARTBaudRate_38400_H 0x02
< .DEFINE C_UARTBaudRate_38400_L 0x80
< .DEFINE C_UARTBaudRate_48000_H 0x02
< .DEFINE C_UARTBaudRate_48000_L 0x00
< .DEFINE C_UARTBaudRate_51200_H 0x01
< .DEFINE C_UARTBaudRate_51200_L 0xE0
< .DEFINE C_UARTBaudRate_57600_H 0x01
< .DEFINE C_UARTBaudRate_57600_L 0xAA
< .DEFINE C_UARTBaudRate_96000_H 0x01 // Daufault
< .DEFINE C_UARTBaudRate_96000_L 0x00
< .DEFINE C_UARTBaudRate_102400_H 0x00
< .DEFINE C_UARTBaudRate_102400_L 0xF0
< .DEFINE C_UARTBaudRate_115200_H 0x00
< .DEFINE C_UARTBaudRate_115200_L 0xD5
< .endif
< // P_UART_Command1
< // Write only
< .DEFINE C_ParityEnable 0x0004
< .DEFINE C_EvenParity 0x0008
< .DEFINE C_InternalReset 0x0020
< .DEFINE C_TxIRQEnable 0x0040
< .DEFINE C_RxIRQEnable 0x0080
<
< // P_UART_Command2
< // Read
< .DEFINE C_ParityError 0x0008
< .DEFINE C_OverrunError 0x0010
< .DEFINE C_FrameError 0x0020
< .DEFINE C_TxReady 0x0040
< .DEFINE C_RxReady 0x0080
< //Write
< .DEFINE C_EnableTx 0x0040
< .DEFINE C_EnableRx 0x0080
<
.external _SP_SIOSendAByte,_SP_SIOReadAByte
.external _Addr,_Ret
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