📄 hardware.lst
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/////////////////////////////////////////////////////////////////
// Note: This register map to the P_INT_Ctrl(0x7010)
// User's interrupt setting have to combine with this register
// while co-work with SACM library.
//
// See. following function for example:
// F_SP_SACM_A2000_Init_:
// F_SP_SACM_S480_Init_:
// F_SP_SACM_S240_Init_:
// F_SP_SACM_MS01_Init_:
// F_SP_SACM_DVR_Init_:
//////////////////////////////////////////////////
0000064F .IRAM
.PUBLIC R_InterruptStatus
0000064F 00 00 .VAR R_InterruptStatus = 0 //
//////////////////////////////////////////////////
.define C_RampDelayTime 32
.define C_QueueSize 144
00000650 00 00 .VAR R_Queue
00000651 00 00 00 00 .DW C_QueueSize-1 DUP(0)
00 00 00 00
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00 00 00 00
00 00
000006E0 00 00 .VAR R_ReadIndex
000006E1 00 00 .VAR R_WriteIndex
00009E5B .CODE
///////////////////////////////////////////
// Function: Initial Queue
// Destory: R1,R2
///////////////////////////////////////////
_SP_InitQueue: .PROC
_SP_InitQueue_A2000:
_SP_InitQueue_S480:
_SP_InitQueue_S240:
_SP_InitQueue_MS01:
_SP_InitQueue_DVR:
F_SP_InitQueue_A2000:
F_SP_InitQueue_S480:
F_SP_InitQueue_S240:
F_SP_InitQueue_MS01:
F_SP_InitQueue_DVR:
F_SP_InitQueue:
00009E5B 09 93 50 06 R1 = R_Queue
00009E5D 40 94 R2 = 0
L_ClearQueueLoop?:
00009E5E D1 D4 [R1++] = R2
00009E5F 09 43 E0 06 cmp R1, R_Queue+C_QueueSize
00009E61 44 4E jne L_ClearQueueLoop?
00009E62 40 92 R1 = 0
00009E63 19 D3 E0 06 [R_ReadIndex] = R1
00009E65 19 D3 E1 06 [R_WriteIndex] = R1
00009E67 90 9A RETF
.ENDP
///////////////////////////////////////////
// Function: Get a data form Queue
// Output: R1: Data
// R2: return value
// Destory: R1,R2
///////////////////////////////////////////
F_SP_ReadQueue_A2000:
F_SP_ReadQueue_S480:
F_SP_ReadQueue_S240:
F_SP_ReadQueue_MS01:
F_SP_ReadQueue_DVR:
F_SP_ReadQueue:
00009E68 12 95 E0 06 R2 = [R_ReadIndex]
00009E6A 12 45 E1 06 cmp R2,[R_WriteIndex]
00009E6C 0D 5E je L_RQ_QueueEmpty
00009E6D 0A 05 50 06 R2 += R_Queue // get queue data address
00009E6F C2 92 R1 = [R2]
00009E70 12 95 E0 06 R2 = [R_ReadIndex]
00009E72 41 04 R2 += 1
00009E73 0A 45 90 00 cmp R2, C_QueueSize
00009E75 01 4E jne L_RQ_NotQueueBottom
00009E76 40 94 R2 = 0
L_RQ_NotQueueBottom:
00009E77 1A D5 E0 06 [R_ReadIndex] = R2
//r2 = 0x0000 // get queue data
00009E79 90 9A retf
L_RQ_QueueEmpty:
//r2 = 0x8000 // queue empty
00009E7A 90 9A retf
///////////////////////////////////////////
// Function: Get a data from Queue but do
// not change queue index
// R1: output
// Destory: R1,R2
///////////////////////////////////////////
F_SP_ReadQueue_NIC:
F_SP_ReadQueue_NIC_A2000:
F_SP_ReadQueue_NIC_S480:
F_SP_ReadQueue_NIC_S240:
F_SP_ReadQueue_NIC_MS01:
F_SP_ReadQueue_NIC_DVR:
00009E7B 12 95 E0 06 R2 = [R_ReadIndex]
00009E7D 12 45 E1 06 cmp R2,[R_WriteIndex]
00009E7F 03 5E je L_RQ_QueueEmpty?
00009E80 0A 05 50 06 R2 += R_Queue // get queue data index
00009E82 C2 92 R1 = [R2]
L_RQ_QueueEmpty?:
00009E83 90 9A RETF
///////////////////////////////////////////
// Function: Put a data to Queue
// R1: Input
// Destory: R1,R2
///////////////////////////////////////////
F_SP_WriteQueue_A2000:
F_SP_WriteQueue_S480:
F_SP_WriteQueue_S240:
F_SP_WriteQueue_MS01:
F_SP_WriteQueue_DVR:
F_SP_WriteQueue:
00009E84 12 95 E1 06 R2 = [R_WriteIndex] // put data to queue
00009E86 0A 05 50 06 R2 += R_Queue
00009E88 C2 D2 [R2] = R1
00009E89 12 95 E1 06 R2 = [R_WriteIndex]
00009E8B 41 04 R2 += 1
00009E8C 0A 45 90 00 cmp R2, C_QueueSize
00009E8E 01 4E jne L_WQ_NotQueueBottom
00009E8F 40 94 R2 = 0
L_WQ_NotQueueBottom:
00009E90 1A D5 E1 06 [R_WriteIndex] = R2
00009E92 90 9A RETF
///////////////////////////////////////////
// Function: Test Queue Status
// o/p: R1
// Destory: R1
///////////////////////////////////////////
F_SP_TestQueue_A2000:
F_SP_TestQueue_S480:
F_SP_TestQueue_S240:
F_SP_TestQueue_MS01:
F_SP_TestQueue_DVR:
F_SP_TestQueue:
//... Test Queue Empty ...
00009E93 11 93 E0 06 R1 = [R_ReadIndex]
00009E95 11 43 E1 06 cmp R1,[R_WriteIndex]
00009E97 12 5E je L_TQ_QueueEmpty
//... Test Queue Full ...
00009E98 11 93 E0 06 R1 = [R_ReadIndex] // For N Queue Full: 1.R=0 and W=N-1 2. R<>0 and W=R-1
00009E9A 05 4E jnz L_TQ_JudgeCond2
00009E9B 11 93 E1 06 R1 = [R_WriteIndex]
00009E9D 09 43 8F 00 cmp R1, C_QueueSize-1 // Cond1
00009E9F 08 5E je L_TQ_QueueFull
L_TQ_JudgeCond2:
00009EA0 11 93 E0 06 R1 = [R_ReadIndex]
00009EA2 41 22 R1 -=1
00009EA3 11 43 E1 06 cmp R1,[R_WriteIndex]
00009EA5 02 5E je L_TQ_QueueFull
00009EA6 40 92 r1 = 0 // not Full, not empty
00009EA7 90 9A retf
L_TQ_QueueFull:
00009EA8 41 92 r1 = 1 // full
00009EA9 90 9A retf
L_TQ_QueueEmpty:
00009EAA 42 92 r1 = 2 // empty
00009EAB 90 9A retf
///////////////////////////////////////////////////////////////////////////////
// Function: The partial code of hardware setting of SACM_A2000_Initial()
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