ppc4xx.h

《嵌入式系统设计与实例开发实验教材二源码》Linux内核移植与编译实验

/*
 * BK Id: SCCS/s.ppc4xx.h 1.3 05/17/01 18:14:25 cort
 */
/*
 *
 *    Copyright (c) 1999 Grant Erickson <[e-mail]>
 *
 *    Module name: ppc4xx.h
 *
 *    Description:
 *	A generic include file which pulls in appropriate include files
 *      for specific board types based on configuration settings.
 *
 */

#ifdef __KERNEL__
#ifndef __PPC4XX_H__
#define	__PPC4XX_H__

#include <linux/config.h>

#ifndef __ASSEMBLY__

#if defined(CONFIG_OAK)
#include <asm/oak.h>
#endif

#if defined(CONFIG_WALNUT)
#include <asm/walnut.h>
#endif

/* IO_BASE is for PCI I/O.
 * ISA not supported, just here to resolve copilation.
 */

#define _IO_BASE	0xe8000000	/* The PCI address window */
#define _ISA_MEM_BASE	0
#define PCI_DRAM_OFFSET	0

extern unsigned long isa_io_base;

/*
 * The "residual" board information structure the boot loader passes
 * into the kernel.
 */
extern unsigned char __res[];

/* I don't know if this is general to 4xx, or unique to a specific
 * processor or board.  In any case it is easy to move.
 */
#define PPC4xx_PCI_IO_ADDR	((uint)0xe8000000)
#define PPC4xx_PCI_IO_SIZE	((uint)64*1024)
#define PPC4xx_PCI_CFG_ADDR	((uint)0xeec00000)
#define PPC4xx_PCI_CFG_SIZE	((uint)4*1024)
#define PPC4xx_PCI_LCFG_ADDR	((uint)0xef400000)
#define PPC4xx_PCI_LCFG_SIZE	((uint)4*1024)
#define PPC4xx_ONB_IO_ADDR	((uint)0xef600000)
#define PPC4xx_ONB_IO_SIZE	((uint)4*1024)

#endif /* __ASSEMBLY__ */

/* Device Control Registers unique to 4xx */

#define	DCRN_BEAR	0x090	/* Bus Error Address Register */
#define	DCRN_BESR	0x091	/* Bus Error Syndrome Register */
#define	  BESR_DSES    	0x80000000	/* Data-Side Error Status */
#define	  BESR_DMES	0x40000000	/* DMA Error Status */
#define	  BESR_RWS	0x20000000	/* Read/Write Status */
#define	  BESR_ETMASK	0x1C000000	/* Error Type */
#define	    ET_PROT	0
#define	    ET_PARITY	1
#define	    ET_NCFG	2
#define	    ET_BUSERR	4
#define	    ET_BUSTO	6
#define DCRN_CHCR0	0x0B1	/* Chip Control Register 1                    */
#define DCRN_CHCR1	0x0B2	/* Chip Control Register 2                    */
#define DCRN_CHPSR	0x0B4	/* Chip Pin Strapping                         */
#define DCRN_CPMER	0x0B9	/* CPM Enable                                 */
#define DCRN_CPMFR	0x0BA	/* CPM Force                                  */
#define   CPM_IIC	0x80000000  /* IIC interface                          */
#define   CPM_PCI	0x40000000  /* PCI bridge                             */
#define   CPM_CPU	0x20000000  /* processor core                         */
#define   CPM_DMA	0x10000000  /* DMA controller                         */
#define   CPM_BRG	0x08000000  /* PLB to OPB bridge                      */
#define   CPM_DCP	0x04000000  /* CodePack                               */
#define   CPM_EBC	0x02000000  /* ROM/SRAM peripheral controller         */
#define   CPM_SDRAM	0x01000000  /* SDRAM memory controller                */
#define   CPM_PLB	0x00800000  /* PLB bus arbiter                        */
#define   CPM_GPIO	0x00400000  /* General Purpose IO (??)                */
#define   CPM_UART0	0x00200000  /* serial port 0                          */
#define   CPM_UART1	0x00100000  /* serial port 1                          */
#define   CPM_UIC	0x00080000  /* Universal Interrupt Controller         */
#define   CPM_TMRCLK	0x00040000  /* CPU timers                             */
#define   CPM_EMAC_MM	0x00020000  /* on-chip ethernet MM unit               */
#define   CPM_EMAC_RM	0x00010000  /* on-chip ethernet RM unit               */
#define   CPM_EMAC_TM	0x00008000  /* on-chip ethernet TM unit               */
#define DCRN_CPMSR	0x0B8	/* CPM Status                                 */

#define	DCRN_DMACR0	0x100	/* DMA Channel Control Register 0             */
#define	DCRN_DMACT0	0x101	/* DMA Count Register 0                       */
#define	DCRN_DMADA0	0x102	/* DMA Destination Address Register 0         */
#define	DCRN_DMASA0	0x103	/* DMA Source Address Register 0              */
#define DCRN_ASG0	0x104	/* DMA Scatter/Gather Descriptor Addr 0       */

#define	DCRN_DMACR1	0x108	/* DMA Channel Control Register 1             */
#define	DCRN_DMACT1	0x109	/* DMA Count Register 1                       */
#define	DCRN_DMADA1	0x10A	/* DMA Destination Address Register 1         */
#define	DCRN_DMASA1	0x10B	/* DMA Source Address Register 1              */
#define DCRN_ASG1	0x10C	/* DMA Scatter/Gather Descriptor Addr 1       */

#define	DCRN_DMACR2	0x110	/* DMA Channel Control Register 2             */
#define	DCRN_DMACT2	0x111	/* DMA Count Register 2                       */
#define	DCRN_DMADA2	0x112	/* DMA Destination Address Register 2         */
#define	DCRN_DMASA2	0x113	/* DMA Source Address Register 2              */
#define DCRN_ASG2	0x114	/* DMA Scatter/Gather Descriptor Addr 2       */

#define	DCRN_DMACR3	0x118	/* DMA Channel Control Register 3             */
#define	DCRN_DMACT3	0x119	/* DMA Count Register 3                       */
#define	DCRN_DMADA3	0x11A	/* DMA Destination Address Register 3         */
#define	DCRN_DMASA3	0x11B	/* DMA Source Address Register 3              */
#define DCRN_ASG3	0x11C	/* DMA Scatter/Gather Descriptor Addr 3       */

#define	DCRN_DMASR	0x120	/* DMA Status Register                        */
#define DCRN_ASGC	0x123	/* DMA Scatter/Gather Command                 */
#define DCRN_ADR	0x124	/* DMA Address Decode                         */

#define DCRN_SLP        0x125   /* DMA Sleep Register                         */
#define DCRN_POL        0x126   /* DMA Polarity Register                      */


#define DCRN_EBCCFGADR	0x012	/* Peripheral Controller Address              */
#define DCRN_EBCCFGDATA	0x013	/* Peripheral Controller Data                 */
#define	DCRN_EXISR	0x040    /* External Interrupt Status Register */
#define	DCRN_EXIER	0x042    /* External Interrupt Enable Register */
#define	  EXIER_CIE	0x80000000	/* Critical Interrupt Enable */
#define	  EXIER_SRIE	0x08000000	/* Serial Port Rx Int. Enable */
#define	  EXIER_STIE	0x04000000	/* Serial Port Tx Int. Enable */
#define	  EXIER_JRIE	0x02000000	/* JTAG Serial Port Rx Int. Enable */
#define	  EXIER_JTIE	0x01000000	/* JTAG Serial Port Tx Int. Enable */
#define	  EXIER_D0IE	0x00800000	/* DMA Channel 0 Interrupt Enable */
#define	  EXIER_D1IE	0x00400000	/* DMA Channel 1 Interrupt Enable */
#define	  EXIER_D2IE	0x00200000	/* DMA Channel 2 Interrupt Enable */
#define	  EXIER_D3IE	0x00100000	/* DMA Channel 3 Interrupt Enable */