sgihpc.h

《嵌入式系统设计与实例开发实验教材二源码》Linux内核移植与编译实验

/* $Id: sgihpc.h,v 1.2 1999/12/06 23:13:21 ralf Exp $
 *
 * sgihpc.h: Various HPC I/O controller defines.  The HPC is basically
 *           the approximate functional equivalent of the Sun SYSIO
 *           on SGI INDY machines.
 *
 * Copyright (C) 1996 David S. Miller ([e-mail])
 * Copyright (C) 1998 Ralf Baechle ([e-mail])
 */
#ifndef _MIPS_SGIHPC_H
#define _MIPS_SGIHPC_H

#include <asm/page.h>

extern int sgi_has_ioc2; /* to know if we have older ioc1 or ioc2. */
extern int sgi_guiness;  /* GUINESS or FULLHOUSE machine. */
extern int sgi_boardid;  /* Board revision. */

/* An HPC dma descriptor. */
struct hpc_dma_desc {
	unsigned int pbuf;      /* physical address of data buffer */
	unsigned int cntinfo;   /* counter and info bits */
#define HPCDMA_EOX    0x80000000 /* last desc in chain for tx */
#define HPCDMA_EOR    0x80000000 /* last desc in chain for rx */
#define HPCDMA_EOXP   0x40000000 /* end of packet for tx */
#define HPCDMA_EORP   0x40000000 /* end of packet for rx */
#define HPCDMA_XIE    0x20000000 /* irq generated when at end of this desc */
#define HPCDMA_XIU    0x01000000 /* Tx buffer in use by CPU. */
#define HPCDMA_EIPC   0x00ff0000 /* SEEQ ethernet special xternal bytecount */
#define HPCDMA_ETXD   0x00008000 /* set to one by HPC when packet tx'd */
#define HPCDMA_OWN    0x00004000 /* Denotes ring buffer ownership on rx */
#define HPCDMA_BCNT   0x00003fff /* size in bytes of this dma buffer */

	unsigned int pnext;     /* paddr of next hpc_dma_desc if any */
};

typedef volatile unsigned int hpcreg;

/* HPC1 stuff. */

/* HPC3 stuff. */

/* The set of regs for each HPC3 pbus dma channel. */
struct hpc3_pbus_dmacregs {
	hpcreg pbdma_bptr; /* pbus dma channel buffer ptr */
	hpcreg pbdma_dptr; /* pbus dma channel desc ptr */
	char _unused1[PAGE_SIZE - (2 * sizeof(hpcreg))]; /* padding */
	hpcreg pbdma_ctrl; /* pbus dma channel control reg */
#define HPC3_PDMACTRL_SEL  0x00000002 /* little endian transfer */
#define HPC3_PDMACTRL_RCV  0x00000004 /* direction is receive */
#define HPC3_PDMACTRL_FLSH 0x00000008 /* enable flush for receive DMA */
#define HPC3_PDMACTRL_ACT  0x00000010 /* start dma transfer */
#define HPC3_PDMACTRL_LD   0x00000020 /* load enable for ACT */
#define HPC3_PDMACTRL_RT   0x00000040 /* Use realtime GIO bus servicing */
#define HPC3_PDMACTRL_HW   0x0000ff00 /* DMA High-water mark */
#define HPC3_PDMACTRL_FB   0x003f0000 /* Ptr to beginning of fifo */
#define HPC3_PDMACTRL_FE   0x3f000000 /* Ptr to end of fifo */

	char _unused2[PAGE_SIZE - (sizeof(hpcreg))]; /* padding */
};

/* The HPC3 scsi registers, this does not include external ones. */
struct hpc3_scsiregs {
	hpcreg cbptr;   /* current dma buffer ptr, diagnostic use only */
	hpcreg ndptr;   /* next dma descriptor ptr */
	char _unused1[PAGE_SIZE - (2 * sizeof(hpcreg))]; /* padding */
	hpcreg bcd;     /* byte count info */
#define HPC3_SBCD_BCNTMSK 0x00003fff /* bytes to transfer from/to memory */
#define HPC3_SBCD_XIE     0x00004000 /* Send IRQ when done with cur buf */
#define HPC3_SBCD_EOX     0x00008000 /* Indicates this is last buf in chain */

	hpcreg ctrl;    /* control register */
#define HPC3_SCTRL_IRQ    0x01 /* IRQ asserted, either dma done or parity */
#define HPC3_SCTRL_ENDIAN 0x02 /* DMA endian mode, 0=big 1=little */
#define HPC3_SCTRL_DIR    0x04 /* DMA direction, 1=dev2mem 0=mem2dev */
#define HPC3_SCTRL_FLUSH  0x08 /* Tells HPC3 to flush scsi fifos */
#define HPC3_SCTRL_ACTIVE 0x10 /* SCSI DMA channel is active */
#define HPC3_SCTRL_AMASK  0x20 /* DMA active inhibits PIO */
#define HPC3_SCTRL_CRESET 0x40 /* Resets dma channel and external controller */
#define HPC3_SCTRL_PERR   0x80 /* Bad parity on HPC3 iface to scsi controller */

	hpcreg gfptr;   /* current GIO fifo ptr */
	hpcreg dfptr;   /* current device fifo ptr */
	hpcreg dconfig; /* DMA configuration register */
#define HPC3_SDCFG_HCLK 0x00001 /* Enable DMA half clock mode */
#define HPC3_SDCFG_D1   0x00006 /* Cycles to spend in D1 state */
#define HPC3_SDCFG_D2   0x00038 /* Cycles to spend in D2 state */
#define HPC3_SDCFG_D3   0x001c0 /* Cycles to spend in D3 state */
#define HPC3_SDCFG_HWAT 0x00e00 /* DMA high water mark */
#define HPC3_SDCFG_HW   0x01000 /* Enable 16-bit halfword DMA accesses to scsi */
#define HPC3_SDCFG_SWAP 0x02000 /* Byte swap all DMA accesses */
#define HPC3_SDCFG_EPAR 0x04000 /* Enable parity checking for DMA */
#define HPC3_SDCFG_POLL 0x08000 /* hd_dreq polarity control */
#define HPC3_SDCFG_ERLY 0x30000 /* hd_dreq behavior control bits */

	hpcreg pconfig; /* PIO configuration register */
#define HPC3_SPCFG_P3   0x0003 /* Cycles to spend in P3 state */
#define HPC3_SPCFG_P2W  0x001c /* Cycles to spend in P2 state for writes */
#define HPC3_SPCFG_P2R  0x01e0 /* Cycles to spend in P2 state for reads */
#define HPC3_SPCFG_P1   0x0e00 /* Cycles to spend in P1 state */
#define HPC3_SPCFG_HW   0x1000 /* Enable 16-bit halfword PIO accesses to scsi */
#define HPC3_SPCFG_SWAP 0x2000 /* Byte swap all PIO accesses */
#define HPC3_SPCFG_EPAR 0x4000 /* Enable parity checking for PIO */
#define HPC3_SPCFG_FUJI 0x8000 /* Fujitsu scsi controller mode for faster dma/pio */

	char _unused2[PAGE_SIZE - (6 * sizeof(hpcreg))]; /* padding */
};

/* SEEQ ethernet HPC3 registers, only one seeq per HPC3. */
struct hpc3_ethregs {
	/* Receiver registers. */
	hpcreg rx_cbptr;   /* current dma buffer ptr, diagnostic use only */
	hpcreg rx_ndptr;   /* next dma descriptor ptr */
	char _unused1[PAGE_SIZE - (2 * sizeof(hpcreg))]; /* padding */
	hpcreg rx_bcd;     /* byte count info */
#define HPC3_ERXBCD_BCNTMSK 0x00003fff /* bytes to be sent to memory */
#define HPC3_ERXBCD_XIE     0x20000000 /* HPC3 interrupts cpu at end of this buf */
#define HPC3_ERXBCD_EOX     0x80000000 /* flags this as end of descriptor chain */

	hpcreg rx_ctrl;    /* control register */
#define HPC3_ERXCTRL_STAT50 0x0000003f /* Receive status reg bits of Seeq8003 */
#define HPC3_ERXCTRL_STAT6  0x00000040 /* Rdonly irq status */
#define HPC3_ERXCTRL_STAT7  0x00000080 /* Rdonlt old/new status bit from Seeq */
#define HPC3_ERXCTRL_ENDIAN 0x00000100 /* Endian for dma channel, little=1 big=0 */
#define HPC3_ERXCTRL_ACTIVE 0x00000200 /* Tells if DMA transfer is in progress */
#define HPC3_ERXCTRL_AMASK  0x00000400 /* Tells if ACTIVE inhibits PIO's to hpc3 */
#define HPC3_ERXCTRL_RBO    0x00000800 /* Receive buffer overflow if set to 1 */

	hpcreg rx_gfptr;   /* current GIO fifo ptr */
	hpcreg rx_dfptr;   /* current device fifo ptr */
	hpcreg _unused2;   /* padding */
	hpcreg rx_reset;   /* reset register */
#define HPC3_ERXRST_CRESET 0x1 /* Reset dma channel and external controller */
#define HPC3_ERXRST_CLRIRQ 0x2 /* Clear channel interrupt */
#define HPC3_ERXRST_LBACK  0x4 /* Enable diagnostic loopback mode of Seeq8003 */

	hpcreg rx_dconfig; /* DMA configuration register */
#define HPC3_ERXDCFG_D1    0x0000f /* Cycles to spend in D1 state for PIO */
#define HPC3_ERXDCFG_D2    0x000f0 /* Cycles to spend in D2 state for PIO */
#define HPC3_ERXDCFG_D3    0x00f00 /* Cycles to spend in D3 state for PIO */
#define HPC3_ERXDCFG_WCTRL 0x01000 /* Enable writes of desc into ex ctrl port */
#define HPC3_ERXDCFG_FRXDC 0x02000 /* Clear eop stat bits upon rxdc, hw seeq fix */
#define HPC3_ERXDCFG_FEOP  0x04000 /* Bad packet marker timeout enable */
#define HPC3_ERXDCFG_FIRQ  0x08000 /* Another bad packet timeout enable */
#define HPC3_ERXDCFG_PTO   0x30000 /* Programmed timeout value for above two */

	hpcreg rx_pconfig; /* PIO configuration register */
#define HPC3_ERXPCFG_P1    0x000f /* Cycles to spend in P1 state for PIO */
#define HPC3_ERXPCFG_P2    0x00f0 /* Cycles to spend in P2 state for PIO */
#define HPC3_ERXPCFG_P3    0x0f00 /* Cycles to spend in P3 state for PIO */
#define HPC3_ERXPCFG_TST   0x1000 /* Diagnistic ram test feature bit */

	char _unused3[PAGE_SIZE - (8 * sizeof(hpcreg))]; /* padding */

	/* Transmitter registers. */
	hpcreg tx_cbptr;   /* current dma buffer ptr, diagnostic use only */
	hpcreg tx_ndptr;   /* next dma descriptor ptr */
	char _unused4[PAGE_SIZE - (2 * sizeof(hpcreg))]; /* padding */
	hpcreg tx_bcd;     /* byte count info */
#define HPC3_ETXBCD_BCNTMSK 0x00003fff /* bytes to be read from memory */
#define HPC3_ETXBCD_ESAMP   0x10000000 /* if set, too late to add descriptor */
#define HPC3_ETXBCD_XIE     0x20000000 /* Interrupt cpu at end of cur desc */
#define HPC3_ETXBCD_EOP     0x40000000 /* Last byte of cur buf is end of packet */
#define HPC3_ETXBCD_EOX     0x80000000 /* This buf is the end of desc chain */

	hpcreg tx_ctrl;    /* control register */
#define HPC3_ETXCTRL_STAT30 0x0000000f /* Rdonly copy of seeq tx stat reg */
#define HPC3_ETXCTRL_STAT4  0x00000010 /* Indicate late collision occurred */
#define HPC3_ETXCTRL_STAT75 0x000000e0 /* Rdonly irq status from seeq */
#define HPC3_ETXCTRL_ENDIAN 0x00000100 /* Dma channel endian mode, 1=little 0=big */
#define HPC3_ETXCTRL_ACTIVE 0x00000200 /* DMA tx channel is active */
#define HPC3_ETXCTRL_AMASK  0x00000400 /* Indicates ACTIVE inhibits PIO's */

	hpcreg tx_gfptr;   /* current GIO fifo ptr */
	hpcreg tx_dfptr;   /* current device fifo ptr */
	char _unused5[PAGE_SIZE - (4 * sizeof(hpcreg))]; /* padding */
};

struct hpc3_regs {
	/* First regs for the PBUS 8 dma channels. */
	struct hpc3_pbus_dmacregs pbdma[8];

	/* Now the HPC scsi registers, we get two scsi reg sets. */
	struct hpc3_scsiregs scsi_chan0, scsi_chan1;

	/* The SEEQ hpc3 ethernet dma/control registers. */
	struct hpc3_ethregs ethregs;