at9200.h

RT-Thread是发展中的下一代微内核嵌入式实时操作系统

/*UART relevant regs off*/
#define AT9200_UART_CR_OFF   0x00  /*(UART)Control Register*/
#define AT9200_UART_MR_OFF   0x04  /*(UART)Mode Register*/
#define AT9200_UART_IER_OFF  0x08  /*(UART)Interrupt Enable Register*/
#define AT9200_UART_IDR_OFF  0x0C  /*(UART)Interrupt Disable Register*/
#define AT9200_UART_IMR_OFF  0x10  /*(UART)Interrupt Mask Register*/
#define AT9200_UART_CSR_OFF  0x14  /*(UART)Channel Status Register*/
#define AT9200_UART_RHR_OFF  0x18  /*(UART)Receiver Holding Register*/
#define AT9200_UART_THR_OFF  0x1C  /*(UART)Transmitter Holding Register*/
#define AT9200_UART_BRGR_OFF 0x20  /*(UART)Baud Rate Generator Register*/  /*the upper 9 regs are the same in UART_x & UART_DBG*/
#define AT9200_UART_RTOR_OFF 0x24  /*(UART)Receiver Time-out Register*/
#define AT9200_UART_TTGR_OFF 0x28  /*(UART)Transmitter Time-guard Register*/

/*UART pins*/
#define UARTDBG_TXD          31
#define UARTDBG_RXD          30
#define UART0_TXD            17
#define UART0_RXD            18
#define UART1_TXD            20
#define UART1_RXD            21
#define UART2_TXD            23
#define UART2_RXD            22
#define UART3_TXD            05
#define UART3_RXD            06

/*PIOD relevant regs*/
#define AT9200_PIOD_PDSR     0xFFFFFA3C
#define AT9200_PIOD_CODR     0xFFFFFA34
#define AT9200_PIOD_OWER     0xFFFFFAA0
#define AT9200_PIOD_MDER     0xFFFFFA50
#define AT9200_PIOD_IMR      0xFFFFFA48
#define AT9200_PIOD_IER      0xFFFFFA40
#define AT9200_PIOD_ODSR     0xFFFFFA38
#define AT9200_PIOD_SODR     0xFFFFFA30
#define AT9200_PIOD_PER      0xFFFFFA00
#define AT9200_PIOD_OWDR     0xFFFFFAA4
#define AT9200_PIOD_PPUER    0xFFFFFA64
#define AT9200_PIOD_MDDR     0xFFFFFA54
#define AT9200_PIOD_ISR      0xFFFFFA4C
#define AT9200_PIOD_IDR      0xFFFFFA44
#define AT9200_PIOD_PDR      0xFFFFFA04
#define AT9200_PIOD_ODR      0xFFFFFA14
#define AT9200_PIOD_OWSR     0xFFFFFAA8
#define AT9200_PIOD_ABSR     0xFFFFFA78
#define AT9200_PIOD_ASR      0xFFFFFA70
#define AT9200_PIOD_PPUSR    0xFFFFFA68
#define AT9200_PIOD_PPUDR    0xFFFFFA60
#define AT9200_PIOD_MDSR     0xFFFFFA58
#define AT9200_PIOD_PSR      0xFFFFFA08
#define AT9200_PIOD_OER      0xFFFFFA10
#define AT9200_PIOD_OSR      0xFFFFFA18
#define AT9200_PIOD_IFER     0xFFFFFA20
#define AT9200_PIOD_BSR      0xFFFFFA74
#define AT9200_PIOD_IFDR     0xFFFFFA24
#define AT9200_PIOD_IFSR     0xFFFFFA28
/*PIOC relevant regs*/
#define AT9200_PIOC_IFDR     0xFFFFF824
#define AT9200_PIOC_ODR      0xFFFFF814
#define AT9200_PIOC_ABSR     0xFFFFF878
#define AT9200_PIOC_SODR     0xFFFFF830
#define AT9200_PIOC_IFSR     0xFFFFF828
#define AT9200_PIOC_CODR     0xFFFFF834
#define AT9200_PIOC_ODSR     0xFFFFF838
#define AT9200_PIOC_IER      0xFFFFF840
#define AT9200_PIOC_IMR      0xFFFFF848
#define AT9200_PIOC_OWDR     0xFFFFF8A4
#define AT9200_PIOC_MDDR     0xFFFFF854
#define AT9200_PIOC_PDSR     0xFFFFF83C
#define AT9200_PIOC_IDR      0xFFFFF844
#define AT9200_PIOC_ISR      0xFFFFF84C
#define AT9200_PIOC_PDR      0xFFFFF804
#define AT9200_PIOC_OWSR     0xFFFFF8A8
#define AT9200_PIOC_OWER     0xFFFFF8A0
#define AT9200_PIOC_ASR      0xFFFFF870
#define AT9200_PIOC_PPUSR    0xFFFFF868
#define AT9200_PIOC_PPUDR    0xFFFFF860
#define AT9200_PIOC_MDSR     0xFFFFF858
#define AT9200_PIOC_MDER     0xFFFFF850
#define AT9200_PIOC_IFER     0xFFFFF820
#define AT9200_PIOC_OSR      0xFFFFF818
#define AT9200_PIOC_OER      0xFFFFF810
#define AT9200_PIOC_PSR      0xFFFFF808
#define AT9200_PIOC_PER      0xFFFFF800
#define AT9200_PIOC_BSR      0xFFFFF874
#define AT9200_PIOC_PPUER    0xFFFFF864
/*PIOB relevant regs*/
#define AT9200_PIOB_OWSR     0xFFFFF6A8
#define AT9200_PIOB_PPUSR    0xFFFFF668
#define AT9200_PIOB_PPUDR    0xFFFFF660
#define AT9200_PIOB_MDSR     0xFFFFF658
#define AT9200_PIOB_MDER     0xFFFFF650
#define AT9200_PIOB_IMR      0xFFFFF648
#define AT9200_PIOB_OSR      0xFFFFF618
#define AT9200_PIOB_OER      0xFFFFF610
#define AT9200_PIOB_PSR      0xFFFFF608
#define AT9200_PIOB_PER      0xFFFFF600
#define AT9200_PIOB_BSR      0xFFFFF674
#define AT9200_PIOB_PPUER    0xFFFFF664
#define AT9200_PIOB_IFDR     0xFFFFF624
#define AT9200_PIOB_ODR      0xFFFFF614
#define AT9200_PIOB_ABSR     0xFFFFF678
#define AT9200_PIOB_ASR      0xFFFFF670
#define AT9200_PIOB_IFER     0xFFFFF620
#define AT9200_PIOB_IFSR     0xFFFFF628
#define AT9200_PIOB_SODR     0xFFFFF630
#define AT9200_PIOB_ODSR     0xFFFFF638
#define AT9200_PIOB_CODR     0xFFFFF634
#define AT9200_PIOB_PDSR     0xFFFFF63C
#define AT9200_PIOB_OWER     0xFFFFF6A0
#define AT9200_PIOB_IER      0xFFFFF640
#define AT9200_PIOB_OWDR     0xFFFFF6A4
#define AT9200_PIOB_MDDR     0xFFFFF654
#define AT9200_PIOB_ISR      0xFFFFF64C
#define AT9200_PIOB_IDR      0xFFFFF644
#define AT9200_PIOB_PDR      0xFFFFF604

/*PIOA relevant regs*/
#define AT9200_PIOA_IMR      0xFFFFF448  /*(PIOA) Interrupt Mask Register      */
#define AT9200_PIOA_IER      0xFFFFF440  /*(PIOA) Interrupt Enable Register    */
#define AT9200_PIOA_OWDR     0xFFFFF4A4  /*(PIOA) Output Write Disable Register*/
#define AT9200_PIOA_ISR      0xFFFFF44C  /*(PIOA) Interrupt Status Register    */
#define AT9200_PIOA_PPUDR    0xFFFFF460  /*(PIOA) Pull-up Disable Register     */
#define AT9200_PIOA_MDSR     0xFFFFF458  /*(PIOA) Multi-driver Status Register */
#define AT9200_PIOA_MDER     0xFFFFF450  /*(PIOA) Multi-driver Enable Register */
#define AT9200_PIOA_PER      0xFFFFF400  /*(PIOA) PIO Enable Register          */
#define AT9200_PIOA_PSR      0xFFFFF408  /*(PIOA) PIO Status Register          */
#define AT9200_PIOA_OER      0xFFFFF410  /*(PIOA) Output Enable Register       */
#define AT9200_PIOA_BSR      0xFFFFF474  /*(PIOA) Select B Register            */
#define AT9200_PIOA_PPUER    0xFFFFF464  /*(PIOA) Pull-up Enable Register      */
#define AT9200_PIOA_MDDR     0xFFFFF454  /*(PIOA) Multi-driver Disable Register*/
#define AT9200_PIOA_PDR      0xFFFFF404  /*(PIOA) PIO Disable Register         */
#define AT9200_PIOA_ODR      0xFFFFF414  /*(PIOA) Output Disable Registerr     */
#define AT9200_PIOA_IFDR     0xFFFFF424  /*(PIOA) Input Filter Disable Register*/
#define AT9200_PIOA_ABSR     0xFFFFF478  /*(PIOA) AB Select Status Register    */
#define AT9200_PIOA_ASR      0xFFFFF470  /*(PIOA) Select A Register            */
#define AT9200_PIOA_PPUSR    0xFFFFF468  /*(PIOA) Pad Pull-up Status Register  */
#define AT9200_PIOA_ODSR     0xFFFFF438  /*(PIOA) Output Data Status Register  */
#define AT9200_PIOA_SODR     0xFFFFF430  /*(PIOA) Set Output Data Register     */
#define AT9200_PIOA_IFSR     0xFFFFF428  /*(PIOA) Input Filter Status Register */
#define AT9200_PIOA_IFER     0xFFFFF420  /*(PIOA) Input Filter Enable Register */
#define AT9200_PIOA_OSR      0xFFFFF418  /*(PIOA) Output Status Register       */
#define AT9200_PIOA_IDR      0xFFFFF444  /*(PIOA) Interrupt Disable Register   */
#define AT9200_PIOA_PDSR     0xFFFFF43C  /*(PIOA) Pin Data Status Register     */
#define AT9200_PIOA_CODR     0xFFFFF434  /*(PIOA) Clear Output Data Register   */
#define AT9200_PIOA_OWSR     0xFFFFF4A8  /*(PIOA) Output Write Status Register */
#define AT9200_PIOA_OWER     0xFFFFF4A0  /*(PIOA) Output Write Enable Register */

/* TC5 relevant regs */
#define AT9200_TC5_CMR		0xFFFA4084	/* (TC5) Channel Mode Register */
#define AT9200_TC5_IDR		0xFFFA40A8	/* (TC5) Interrupt Disable Register */
#define AT9200_TC5_SR		0xFFFA40A0	/* (TC5) Status Register */
#define AT9200_TC5_RB		0xFFFA4098	/* (TC5) Register B */
#define AT9200_TC5_CV		0xFFFA4090	/* (TC5) Counter Value */
#define AT9200_TC5_CCR		0xFFFA4080	/* (TC5) Channel Control Register */
#define AT9200_TC5_IMR		0xFFFA40AC	/* (TC5) Interrupt Mask Register */
#define AT9200_TC5_IER		0xFFFA40A4	/* (TC5) Interrupt Enable Register */
#define AT9200_TC5_RC		0xFFFA409C	/* (TC5) Register C */
#define AT9200_TC5_RA		0xFFFA4094	/* (TC5) Register A */
/* TC4 relevant regs */
#define AT9200_TC4_IMR		0xFFFA406C	/* (TC4) Interrupt Mask Register */
#define AT9200_TC4_IER		0xFFFA4064	/* (TC4) Interrupt Enable Register */
#define AT9200_TC4_RC		0xFFFA405C	/* (TC4) Register C */
#define AT9200_TC4_RA		0xFFFA4054	/* (TC4) Register A */
#define AT9200_TC4_CMR		0xFFFA4044	/* (TC4) Channel Mode Register */
#define AT9200_TC4_IDR		0xFFFA4068	/* (TC4) Interrupt Disable Register */
#define AT9200_TC4_SR		0xFFFA4060	/* (TC4) Status Register */
#define AT9200_TC4_RB		0xFFFA4058	/* (TC4) Register B */
#define AT9200_TC4_CV		0xFFFA4050	/* (TC4) Counter Value */
#define AT9200_TC4_CCR		0xFFFA4040	/* (TC4) Channel Control Register */
/* TC3 relevant regs */
#define AT9200_TC3_IMR		0xFFFA402C	/* (TC3) Interrupt Mask Register */
#define AT9200_TC3_CV		0xFFFA4010	/* (TC3) Counter Value */
#define AT9200_TC3_CCR		0xFFFA4000	/* (TC3) Channel Control Register */
#define AT9200_TC3_IER		0xFFFA4024	/* (TC3) Interrupt Enable Register */
#define AT9200_TC3_CMR		0xFFFA4004	/* (TC3) Channel Mode Register */
#define AT9200_TC3_RA		0xFFFA4014	/* (TC3) Register A */
#define AT9200_TC3_RC		0xFFFA401C	/* (TC3) Register C */
#define AT9200_TC3_IDR		0xFFFA4028	/* (TC3) Interrupt Disable Register */
#define AT9200_TC3_RB		0xFFFA4018	/* (TC3) Register B */
#define AT9200_TC3_SR		0xFFFA4020	/* (TC3) Status Register */
/* TCB1 relevant regs */
#define AT9200_TCB1_BCR 	0xFFFA4140	/* (TCB1) TC Block Control Register */
#define AT9200_TCB1_BMR 	0xFFFA4144	/* (TCB1) TC Block Mode Register */
/* TC2 relevant regs */
#define AT9200_TC2_IMR		0xFFFA00AC	/* (TC2) Interrupt Mask Register */
#define AT9200_TC2_IER		0xFFFA00A4	/* (TC2) Interrupt Enable Register */
#define AT9200_TC2_RC		0xFFFA009C	/* (TC2) Register C */
#define AT9200_TC2_RA		0xFFFA0094	/* (TC2) Register A */
#define AT9200_TC2_CMR		0xFFFA0084	/* (TC2) Channel Mode Register */
#define AT9200_TC2_IDR		0xFFFA00A8	/* (TC2) Interrupt Disable Register */
#define AT9200_TC2_SR		0xFFFA00A0	/* (TC2) Status Register */
#define AT9200_TC2_RB		0xFFFA0098	/* (TC2) Register B */
#define AT9200_TC2_CV		0xFFFA0090	/* (TC2) Counter Value */
#define AT9200_TC2_CCR		0xFFFA0080	/* (TC2) Channel Control Register */
/* TC1 relevant regs */
#define AT9200_TC1_IMR		0xFFFA006C	/* (TC1) Interrupt Mask Register */
#define AT9200_TC1_IER		0xFFFA0064	/* (TC1) Interrupt Enable Register */
#define AT9200_TC1_RC		0xFFFA005C	/* (TC1) Register C */
#define AT9200_TC1_RA		0xFFFA0054	/* (TC1) Register A */
#define AT9200_TC1_CMR		0xFFFA0044	/* (TC1) Channel Mode Register */
#define AT9200_TC1_IDR		0xFFFA0068	/* (TC1) Interrupt Disable Register */
#define AT9200_TC1_SR		0xFFFA0060	/* (TC1) Status Register */
#define AT9200_TC1_RB		0xFFFA0058	/* (TC1) Register B */
#define AT9200_TC1_CV		0xFFFA0050	/* (TC1) Counter Value */
#define AT9200_TC1_CCR		0xFFFA0040	/* (TC1) Channel Control Register */
/* TC0 relevant regs */
#define AT9200_TC0_IMR		0xFFFA002C	/* (TC0) Interrupt Mask Register */
#define AT9200_TC0_IER		0xFFFA0024	/* (TC0) Interrupt Enable Register */
#define AT9200_TC0_RC		0xFFFA001C	/* (TC0) Register C */
#define AT9200_TC0_RA		0xFFFA0014	/* (TC0) Register A */
#define AT9200_TC0_CMR		0xFFFA0004	/* (TC0) Channel Mode Register */
#define AT9200_TC0_IDR		0xFFFA0028	/* (TC0) Interrupt Disable Register */
#define AT9200_TC0_SR		0xFFFA0020	/* (TC0) Status Register */
#define AT9200_TC0_RB		0xFFFA0018	/* (TC0) Register B */
#define AT9200_TC0_CV		0xFFFA0010	/* (TC0) Counter Value */
#define AT9200_TC0_CCR		0xFFFA0000	/* (TC0) Channel Control Register */
/* TCB0 relevant regs */
#define AT9200_TCB0_BMR 	0xFFFA00C4	/* (TCB0) TC Block Mode Register */
#define AT9200_TCB0_BCR 	0xFFFA00C0	/* (TCB0) TC Block Control Register */

/*@}*/

#ifdef __cplusplus
}
#endif
#endif  /*#ifndef __AT9200_H__'s end*/