at9200.h

RT-Thread是发展中的下一代微内核嵌入式实时操作系统

/*
 * File      : AT9200.h
 * This file is part of RT-Thread RTOS
 * COPYRIGHT (C) 2006, RT-Thread Develop Team
 *
 * The license and distribution terms for this file may be
 * found in the file LICENSE in this distribution or at
 * http://openlab.rt-thread.com/license/LICENSE
 *
 * Change Logs:
 * Date           Author       Notes
 *                Triseel
 */

#ifndef __AT9200_H__
#define __AT9200_H__

#ifdef __cplusplus
extern "C" {
#endif

/**
 * @addtogroup AT9200
 */
/*@{*/

/*****************************/
/* CPU Mode                  */
/*****************************/
#define USERMODE        0x10
#define FIQMODE         0x11
#define IRQMODE         0x12
#define SVCMODE         0x13
#define ABORTMODE       0x17
#define UNDEFMODE       0x1B
#define MODEMASK        0x1F
#define NOINT           0xC0

struct rt_hw_register
{
	unsigned long r0;
	unsigned long r1;
	unsigned long r2;
	unsigned long r3;
	unsigned long r4;
	unsigned long r5;
	unsigned long r6;
	unsigned long r7;
	unsigned long r8;
	unsigned long r9;
	unsigned long r10;
	unsigned long fp;
	unsigned long ip;
	unsigned long sp;
	unsigned long lr;
	unsigned long pc;
	unsigned long cpsr;
	unsigned long ORIG_r0;
};

#define REG_OUT32(BaseAddr, RegOff, Data)    (	(  *((volatile unsigned int *) (BaseAddr+(RegOff)) ) )=(rt_uint32_t)(Data) )
#define REG_IN32(BaseAddr, RegOff)           (	*((volatile unsigned int *) (BaseAddr+(RegOff)) ) )

#define BMP_ISSET(BmpVal, SpecifiedBit)      (  (BmpVal) & (SpecifiedBit) ? 1 : 0  )
#define BMP_SET(BmpVal, SpecifiedBit)        (  (BmpVal)|= (SpecifiedBit)  )
#define BMP_CLEAR(BmpVal, SpecifiedBit)      (  (BmpVal)&=~(SpecifiedBit)  )

typedef enum IntVec_E
{
	FIQ_VEC=0,
	SYS_VEC,
	PIOA_VEC,
	PIOB_VEC,
	PIOC_VEC,
	PIOD_VEC,
	UART0_VEC,
	UART1_VEC,
	UART2_VEC,
	UART3_VEC,
	MCI_VEC,
	UDP_VEC,
	TWI_VEC,
	SPI_VEC,
	SSC0_VEC,
	SSC1_VEC,
	SSC2_VEC,
	TC0_VEC,
	TC1_VEC,
	TC2_VEC,
	TC4_VEC,
	TC5_VEC,
	UHP_VEC,
	EMAC_VEC,
	IRQ0_VEC,
	IRQ1_VEC,
	IRQ2_VEC,
	IRQ3_VEC,
	IRQ4_VEC,
	IRQ5_VEC,
	IRQ6_VEC,
	MAX_VEC=32,
}IntVec_E;

#define CPU_MASTER_CLK    60825600/*89856000*/

#define SYS_VEC      1
#define PIOA_VEC     2
#define PIOB_VEC     3
#define PIOC_VEC     4
#define UART0_VEC    6
#define UART1_VEC    7
#define UART2_VEC    8
#define UART3_VEC    9
#define TC01_VEC     18
#define TC02_VEC     19
#define TC04_VEC     21
#define EMAC_VEC     24
#define PHY_VEC      25
#define IRQ4_VEC     29

#define SYS_INT_ST_BIT         (1<<0)
#define SYS_INT_DBGUART_BIT    (1<<1)

#define ALL_VEC      0xFFFFFFFF

/*9200 functional regs base addr*/
#define AT9200_BASE_MC       0xFFFFFF00
#define AT9200_BASE_RTC      0xFFFFFE00
#define AT9200_BASE_ST       0xFFFFFD00
#define AT9200_BASE_PMC      0xFFFFFC00
#define AT9200_BASE_CKGR     0xFFFFFC20
#define AT9200_BASE_PIOD     0xFFFFFA00
#define AT9200_BASE_PIOC     0xFFFFF800
#define AT9200_BASE_PIOB     0xFFFFF600
#define AT9200_BASE_PIOA     0xFFFFF400
#define AT9200_BASE_DBGU     0xFFFFF200
#define AT9200_BASE_PDC_DBGU 0xFFFFF300
#define AT9200_BASE_AIC      0xFFFFF000
#define AT9200_BASE_PDC_SPI  0xFFFE0100
#define AT9200_BASE_SPI      0xFFFE0000
#define AT9200_BASE_PDC_SSC2 0xFFFD8100
#define AT9200_BASE_SSC2     0xFFFD8000
#define AT9200_BASE_PDC_SSC1 0xFFFD4100
#define AT9200_BASE_SSC1     0xFFFD4000
#define AT9200_BASE_PDC_SSC0 0xFFFD0100
#define AT9200_BASE_SSC0     0xFFFD0000
#define AT9200_BASE_PDC_US3  0xFFFCC100
#define AT9200_BASE_US3      0xFFFCC000
#define AT9200_BASE_PDC_US2  0xFFFC8100
#define AT9200_BASE_US2      0xFFFC8000
#define AT9200_BASE_PDC_US1  0xFFFC4100
#define AT9200_BASE_US1      0xFFFC4000
#define AT9200_BASE_PDC_US0  0xFFFC0100
#define AT9200_BASE_US0      0xFFFC0000
#define AT9200_BASE_TWI      0xFFFB8000
#define AT9200_BASE_PDC_MCI  0xFFFB4100
#define AT9200_BASE_MCI      0xFFFB4000
#define AT9200_BASE_UDP      0xFFFB0000
#define AT9200_BASE_TC5      0xFFFA4080
#define AT9200_BASE_TC4      0xFFFA4040
#define AT9200_BASE_TC3      0xFFFA4000
#define AT9200_BASE_TCB1     0xFFFA4080
#define AT9200_BASE_TC2      0xFFFA0080
#define AT9200_BASE_TC1      0xFFFA0040
#define AT9200_BASE_TC0      0xFFFA0000
#define AT9200_BASE_TCB0     0xFFFA0000
#define AT9200_BASE_UHP      0x00300000
#define AT9200_BASE_EMAC     0xFFFBC000
#define AT9200_BASE_EBI      0xFFFFFF60
#define AT9200_BASE_SMC2     0xFFFFFF70
#define AT9200_BASE_SDRC     0xFFFFFF90
#define AT9200_BASE_BFC      0xFFFFFFC0

/*AIC relevant regs*/
#define AT9200_AIC_IECR      0xFFFFF120  /*(AIC) Interrupt Enable Command Register */
#define AT9200_AIC_IDCR      0xFFFFF124  /*(AIC) Interrupt Disable Command Register*/
#define AT9200_AIC_ICCR      0xFFFFF128  /*(AIC) Interrupt Clear Command Register  */
#define AT9200_AIC_ISCR      0xFFFFF12C  /*(AIC) Interrupt Set Command Register    */
#define AT9200_AIC_SMR       0xFFFFF000  /*(AIC) Source Mode Register              */
#define AT9200_AIC_EOICR     0xFFFFF130  /*(AIC) End of Interrupt Command Register */
#define AT9200_AIC_DCR       0xFFFFF138  /*(AIC) Debug Control Register (Protect)  */
#define AT9200_AIC_FFER      0xFFFFF140  /*(AIC) Fast Forcing Enable Register      */
#define AT9200_AIC_SVR       0xFFFFF080  /*(AIC) Source Vector Register            */
#define AT9200_AIC_SPU       0xFFFFF134  /*(AIC) Spurious Vector Register          */
#define AT9200_AIC_FFDR      0xFFFFF144  /*(AIC) Fast Forcing Disable Register     */
#define AT9200_AIC_FVR       0xFFFFF104  /*(AIC) FIQ Vector Register               */
#define AT9200_AIC_FFSR      0xFFFFF148  /*(AIC) Fast Forcing Status Register      */
#define AT9200_AIC_IMR       0xFFFFF110  /*(AIC) Interrupt Mask Register           */
#define AT9200_AIC_ISR       0xFFFFF108  /*(AIC) Interrupt Status Register         */
#define AT9200_AIC_IVR       0xFFFFF100  /*(AIC) IRQ Vector Register               */
#define AT9200_AIC_CISR      0xFFFFF114  /*(AIC) Core Interrupt Status Register    */
#define AT9200_AIC_IPR       0xFFFFF10C  /*(AIC) Interrupt Pending Register        */

/*PMC relevant regs*/
#define AT9200_PMC_SCER      0xFFFFFC00  /*(PMC) System Clock Enable Register     */
#define AT9200_PMC_SCDR      0xFFFFFC04  /*(PMC) System Clock Disable Register    */
#define AT9200_PMC_SCSR      0xFFFFFC08  /*(PMC) System Clock Status Register     */
#define AT9200_PMC_PCER      0xFFFFFC10  /*(PMC) Peripheral Clock Enable Register */
#define AT9200_PMC_PCDR      0xFFFFFC14  /*(PMC) Peripheral Clock Disable Register*/
#define AT9200_PMC_PCSR      0xFFFFFC18  /*(PMC) Peripheral Clock Status Register */
#define AT9200_PMC_MCKR      0xFFFFFC30  /*(PMC) Master Clock Register            */
#define AT9200_PMC_IER       0xFFFFFC60  /*(PMC) Interrupt Enable Register        */
#define AT9200_PMC_IDR       0xFFFFFC64  /*(PMC) Interrupt Disable Register       */
#define AT9200_PMC_SR        0xFFFFFC68  /*(PMC) Status Register                  */
#define AT9200_PMC_IMR       0xFFFFFC6C  /*(PMC) Interrupt Mask Register          */

#define AT9200_PMC_PCKR      0xFFFFFC40  /*(PMC) Programmable Clock Register      */

/*ST relevant regs bit*/
#define AT9200_ST_PITS_BIT   0x01  /*reg AT9200_ST_SR*/

/*ST relevant regs*/
#define AT9200_ST_CRTR       0xFFFFFD24  /*(ST) Current Real-time Register   */
#define AT9200_ST_IMR        0xFFFFFD1C  /*(ST) Interrupt Mask Register      */
#define AT9200_ST_IER        0xFFFFFD14  /*(ST) Interrupt Enable Register    */
#define AT9200_ST_RTMR       0xFFFFFD0C  /*(ST) Real-time Mode Register      */
#define AT9200_ST_PIMR       0xFFFFFD04  /*(ST) Period Interval Mode Register*/
#define AT9200_ST_RTAR       0xFFFFFD20  /*(ST) Real-time Alarm Register     */
#define AT9200_ST_IDR        0xFFFFFD18  /*(ST) Interrupt Disable Register   */
#define AT9200_ST_SR         0xFFFFFD10  /*(ST) Status Register              */
#define AT9200_ST_WDMR       0xFFFFFD08  /*(ST) Watchdog Mode Register       */
#define AT9200_ST_CR         0xFFFFFD00  /*(ST) Control Register             */

/*UART relevant regs bit*/
#define AT9200_US_RXRDY_BIT      0x01   /*(UART)Rx ready(reg AT9200_UART_IER_OFF)*/
#define AT9200_US_RSTRX_VAL      0x100  /*(UART)Reset Rx(reg AT9200_UART_CR_OFF)*/
#define AT9200_US_TXEMPTY_VAL    0x200  /*(UART)Tx buf empty(reg AT9200_UART_CSR_OFF)*/